數(shù)電課件第10次課

Review

LatchFlip-FlopSec.7.3Flip-FlopOperatingCharacteristicsCHAPTER7PropagationDelayTimes

Apropagationdelaytimeistheintervaloftimerequiredafteraninputsignalhasbeenappliedfortheresultingoutputchangetooccur.Sec.7.3Flip-FlopOperatingCharacteristicsCHAPTER7PropagationDelayTimesSec.7.3Flip-FlopOperatingCharacteristicsCHAPTER7Set-upTime

Theset-uptimeistheminimumintervalrequiredforthelogiclevelstobemaintainedconstantlyontheinputspriortothetriggeringedgeoftheclockpulseinorderforthelevelstobereliablyclockedintotheflip-flop.Sec.7.3Flip-FlopOperatingCharacteristicsCHAPTER7HoldTime

Theholdtimeistheminimumintervalrequiredforthelogiclevelstoremainontheinputsafterthetriggeringedgeoftheclockpulseinorderforthelevelstobereliablyclockedintotheflip-flop.Sec.7.3Flip-FlopOperatingCharacteristicsCHAPTER7MaximumClockFrequency

Theminimumpulsewidthsforreliablyoperationareusuallyspecifiedbythemanufacturerfortheclock,preset,andclearinputs.

Themaximumclockfrequencyisthehighestrateatwhichaflip-flopcanbereliablytriggered.PulseWidthsSec.7.3Flip-FlopOperatingCharacteristicsCHAPTER7PowerDissipationThepowerdissipationofanydigitalcircuitisthetotalpowerconsumptionofthedevice.Thepowerdissipationisveryimportantinmostapplicationsinwhichthecapacityofthedcsupplyisconcern.Sec.7.4Flip-FlopApplicationsCHAPTER7

ParallelDataStorage

Acommonrequirementindigitalsystemsistostoreseveralbitsofdatafromparallellinessimultaneouslyinagroupofflip-flops.Sec.7.4Flip-FlopApplicationsCHAPTER7

FrequencyDivision

Dividing(reducing)thefrequencyofaperiodicwaveformSec.7.4Flip-FlopApplicationsCHAPTER7

FrequencyDivisionSec.7.4Flip-FlopApplicationsCHAPTER7

FrequencyDivisionSec.7.4Flip-FlopApplicationsCHAPTER7

CountingFigure7–41Flip-flopsusedtogenerateabinarycountsequence.Tworepetitions(00,01,10,11)areshown.Sec.7.4Flip-FlopApplicationsCHAPTER7

Counting

Example7-11Determinetheoutputwaveforms.Sec.7.4Flip-FlopApplicationsCHAPTER7

CountingChapter8

CountersMainContents

SynchronousCounterOperationAsynchronousCounterOperationCascadedCountersCounterDecodingCombinationalcircuitFlip-flopcircuitX1XiZ1ZjQ1QmD1Dm…………inputsignalsignaloutputFlip-flopFlip-flopInputsignalOutputsignalCPSec.8.1AsynchronousCounterOperationCHAPTER8

Thetermasynchronousreferstoeventsthatdonothaveafixedtimerelationshipwitheachotherand,generally,donotoccuratthesametime.Theflip-flopsdonothavethecommonclockpulse.Sec.8.1AsynchronousCounterOperationCHAPTER8A2-BitAsynchronousBinaryCounterFigure8–1A2-bitasynchronousbinarycounter.Sec.8.1AsynchronousCounterOperationCHAPTER8A2-BitAsynchronousBinaryCounterFigure8–2TimingdiagramforthecounterofFigure8–1.

Sec.8.1AsynchronousCounterOperationCHAPTER8A2-BitAsynchronousBinaryCounterBinarystatesequenceforcounterinFigure8-1

ClockPulseQ1Q0Initially001012103114(recycles)00Sec.8.1AsynchronousCounterOperationCHAPTER8A3-BitAsynchronousBinaryCounterStatesequencefora3-bitbinarycounter

ClockPulseQ2Q1Q0Initially00010012010301141005101611071118(recycles)000Sec.8.1AsynchronousCounterOperationCHAPTER8A3-BitAsynchronousBinaryCounterSec.8.1AsynchronousCounterOperationCHAPTER8PropagationDelaySec.8.1AsynchronousCounterOperationCHAPTER8PropagationDelay

Themaximumcumulativedelayinacountermustbelessthantheperiodoftheclockwaveform.Thetotaldelayof3-bitasynchronousbinarycounterisSec.8.1AsynchronousCounterOperationCHAPTER8

Example8-1A4-bitasynchronousbinarycounterisshowninFigure8-5(a).Eachflip-flopisnegativeedge-triggeredandhasapropagationdelayfor10ns.Determinethemaximumclockfrequency.Sec.8.1AsynchronousCounterOperationCHAPTER8

Solution:Forthetotaldelaytime,theeffectofCLK8andCLK16mustpropagatethroughfourflip-flopsbeforeQ3changes,so

ThemaximumclockfrequencyisSec.8.1AsynchronousCounterOperationCHAPTER8AsynchronousDecodeCounters

Themodulusofacounteristhenumberofuniquestatesthroughwhichthecounterwillsequence.Themaximumpossiblenumberofstatesofacounteris2n,wherenisthenumberofflip-flopsinthecounters.Counterscanbedesignedtohaveanumberofstatesintheirsequencethatislessthanthemaximumof2n.Sec.8.1AsynchronousCounterOperationCHAPTER8AsynchronousDecodeCountersFigure8-6DecadeCounter(0000~1010)Sec.8.1AsynchronousCounterOperationCHAPTER8AsynchronousDecodeCounters

Example8-2Showhowanasynchronouscountercanbeimplementedhavingamodulusoftwelvewithastraightbinarysequencefrom0000through1011.Solution:thestateis0000->0001->0010->0011->….->1000->1001->1010->1011->0000->0001Sec.8.1AsynchronousCounterOperationCHAPTER8AsynchronousDecodeCountersFigure8–7Asynchronouslyclockedmodulus-12counterwithasynchronousrecycling.Sec.8.1AsynchronousCounterOperationCHAPTER8The74LS934-BitAsynchronousBinaryCounterSec.8.1AsynchronousCounterOperationCHAPTER8The74LS934-BitAsynchronousBinaryCounterSec.8.1AsynchronousCounterOperationCHAPTER8

Example8-3Showhowthe74LS93canbeusedasamodulus-12counter.Solution:Usingthegatedresetinputs,RO(1)andRO(2)

Sec.8.2SynchronousCounterOperationCHAPTER8

Thetermsynchronousreferstoeventsthathaveafixedtimerelationshipwitheachother.Asynchronouscounterisoneinwhichalltheflip-flopinthecounterareclockedatthesametimebyacommonclockpulse.Sec.8.2SynchronousCounterOperationCHAPTER8

Figure8-11showsa2-bitsynchronousbinarycounter.A2-bitSynchronousBinaryCounterSec.8.2SynchronousCounterOperationCHAPTER8A2-bitSynchronousBinaryCounterFigure8–12Timingdetailsforthe2-bitsynchronouscounteroperation(thepropagationdelaysofbothflip-flopsareassumedtobeequal).Sec.8.2SynchronousCounterOperationCHAPTER8A2-bitSynchronousBinaryCounterFigure8–13TimingdiagramforthecounterofFigure8–11.Sec.8.2SynchronousCounterOperationCHAPTER8A2-bitSynchronousBinaryCounterThestateof2-bitsynchronousbinarycounteris

Sec.8.2SynchronousCounterOperationCHAPTER8A3-bitSynchronousBinaryCounterSec.8.2SynchronousCounterOperationCHAPTER8A3-bitSynchronousBinaryCounterWhenQ0Q1=1,thereisacarrytoQ2Sec.8.2SynchronousCounterOperationCHAPTER8A3-bitSynchronousBinaryCounterClockPulseQ2Q1Q0Initially00010012010301141005101611071118(recycles)000Statesequencefora3-bitbinarycounter

Sec.8.2SynchronousCounterOperationCHAPTER8A4-bitSynchronousBinaryCounterSec.8.2SynchronousCounterOperationCHAPTER8A4-bitSynchronousDecadeCounter

ABCDdecadecounterexhibitsatruncatedbinarysequenceandgoesfrom0000throughthe1001state.Ratherthangoingfromthe1001stateto1010state,itrecyclestothe0000state.Sec.8.2SynchronousCounterOperationCHAPTER8A4-bitSynchronousDecadeCounterFigure8–17AsynchronousBCDdecadecounter.Sec.8.2SynchronousCounterOperationCHAPTER8A4-bitSynchronousDecadeCounterFigure8–18TimingdiagramfortheBCDdecadecounter(Q0istheLSB).Sec.8.2SynchronousCounterOperationCHAPTER8A4-bitSynchronousDecadeCounterJ1=K1=Q0Q3J0=K0=1J2=K2=Q0Q1J3=K3=Q0Q1Q2+Q0Q3Sec.8.2SynchronousCounterOperationCHAPTER8A4-bitSynchronousDecadeCounterClockPulseQ3Q2Q1Q0Initially000010001200103001140100501016011070111810009100110(recycles)0000Sec.8.2SynchronousCounterOperationCHAPTER8The74HC1634-BitSynchronousBinaryCounter

The74HC163isanexampleofanintegratedcircuit4-bitsynchronousbinarycounter.Sec.8.2SynchronousCounterOperationCHAPTER8The74HC1634-BitSynchronousBinaryCounterSec.8.2SynchronousCounterOperationCHAPTER8The74HC162SynchronousBCDDecadeCounterSec.8.2SynchronousCounterOperationCHAPTER8The74HC162SynchronousBCDDecadeCounterSec.8.3Up/DownSynchronousCountersCHAPTER8

Anup/downcounterisonethatiscapableofprogressingineitherdirectionthroughacertainsequence.Anup/downcounter,sometimescalledabidirectionalcounter,canhaveanyspecifiedsequenceofstates.Mostup/downcounterscanbereversedatanypointintheirsequence.Sec.8.3Up/DownSynchronousCountersCHAPTER8Sec.8.3Up/DownSynchronousCountersCHAPTER8

Abasic3-bitup/downsynchronouscounterSec.8.3Up/DownSynchronousCountersCHAPTER8

Abasic3-bitup/downsynchronouscounterSec.8.3Up/DownSynchronousCountersCHAPTER8