集成電路設(shè)計(jì)課件-系統(tǒng)設(shè)計(jì)

1集成電路設(shè)計(jì)第九章

系統(tǒng)設(shè)計(jì)（2）

DesignMethodologies2outlineDesignmethodologies.Kitchentimerexample.3Application

Motivatedby:AbrightideaAmarketopportunityAnemergingmarketAhighgrowthmarketAtechnologicalbreakthroughForexample-wirelesstelephony4Top-LevelDesignflowCreate

SystemSpecificationDevelop

BehaviorModelRefine&Test

BehaviorModelDetermine

Hardware/SoftwarePartitionCharacterizedlibraryofhardware/softwaremacros&interfaceprotocolsSpecify&Develop

HardwareArchitecturalModelDevelop

PrototypeSoftwareRefine&TestArchitecturalModel(Hardware/SoftwareCo-Simulation)SpecifyImplementationBlocksSpecifySoftwareBlock1

SpecificationBlock2

Specification5Block-LevelMethodology6DesignFlowEvolution(ITRS-2003)7DesignmethodologiesEverycompanyhasitsowndesignmethodology.Methodologydependson:sizeofchip;designtimeconstraints;cost/performance;availabletools.8GenericdesignflowArchitecturalSimulationFloorplanRegister-transferDesignLogicDesignCircuitDesignLayoutFunctional/PerformanceVerificationTestabilityDetailedSpecsTapeout9SpecificationandplanningDrivenbycontradictoryimpulses:customer-centricconcernsaboutcost,performance,etc.;forecastsoffeasibilityofcostandperformance.Features,performance,power,etc.maybenegotiatedatearlystagesnegotiationatlaterstagescreatesproblems.10EstimationandplanningEstimationtechniquesvarywithmodule:memoriesmaybegeneratedoncesizeisknown;datapathsmaybeestimatedfrompreviousdesign;controllersarehardtoestimatewithoutdetails.Estimatesmustincludespeed,area,power.11FloorplanningandbudgetingThepurposeofearlyfloorplanningistoestablishbudgetsforeachmajorcomponent:area,delay,power,etc.Theprojectleadermustensurethatbudgetsaremetatalltimes.Ifitbecomesclearthatmeetingabudgetforacomponentisimpossible,thefloorplanmustberedoneASAP.12Circuit/layoutdesignTasks:sizetransistors;drawlayout.Alternativedesignstyles:fullcustomlogic(verytedious);standardcell.Fullcustommostlikelyfordatapaths,leastlikelyforrandomlogicoffcriticalpath.13LogicdesignForcontrollers,goodstateassignmentisusuallyrequiresCADtools.Logicsynthesisisanoption:verygoodfornon-criticallogic;canworkwellforspeed-criticallogic.Logicsynthesissystemmaybesensitivetochangesintheinputspecification.14DesignvalidationMustverify:layout(designrulecheck=DRC);circuitperformance;clockdistribution;functionality;powerconsumption/powerbussing.15TestingAutomatictestpatterngeneration=ATPG.Mustverifythatcircuitcanbetested,generateacompactsetofmanufacturingtestvectors.Testvectorsoftencomprisedofvectorstakenfromsimulation+ATPG-generatedvectors.16TapeoutTapeout:generatingfinalfilesformasks.Shippedtomask-makinghouse.Pre-tapeoutverificationisimportancesinceitwilltakemonthstogetresultsfromfab.Tapeout

party

follows.17KitchentimerchipSimpleexamplewhichillustratesoveralldesignprocess.Kitchentimerkeepstwoindependenttimers:setminutes,seconds.go,clear;Notperformance-sensitive;ispower-sensitive.18Kitchentimersystemtimerchiptimer1timer2gominutessecondsclearseconds19Timerchiparchitecturesketchbuttonsenablesegmentsbuzzercontrollertimer1timer2buzzdisplay20MajordesigndecisionsUsebinary-codeddecimal(BCD)torepresenttimes:allowsdirectdisplayoftimerregistervalues;requiresafewmoreregistersthanbinary,butBCD/7-segmentdecoderismuchsmallerthanbinary/7-segmentdecoder.Usescanneddisplay—sendonlyonedigitatatimetodisplaytoreducewiringbetweencomponents.21Kitchentimercomponenthierarchytimerchipcontrollerbuzztimersdisplaytimer1timer222ComponentinventoryTimers:Holdstimeinregister;couldbeincrement,decrement,clear.

Inputs:incr_seconds[2],incr_minutes[2],go,digit_select.Outputs:done,digit[4].Display:Cyclesthroughdisplayeddigits.Inputs:digit[4].Outputs:enable[4],segments[7].23Componentinventory(cont’d)Buzz:Enablesbuzzsignaluntilstop.Inputs:done,stop.Outputs:buzz.Controller:Generatesallrequiredcontrolsignals.Inputs