超低功耗iCE40 HX系列架構(gòu)圖分析

超低功耗iCE40HX系列架構(gòu)圖分析lattice公司的iCE40HX超低功耗mobileFPGA系列，和其它任何的CPLD或FPGA器件相比，可提供最低的靜態(tài)和動(dòng)態(tài)功耗，大約640到7680個(gè)邏輯單元和觸發(fā)器，每個(gè)器件包含8到32個(gè)RAM區(qū)塊，每個(gè)區(qū)塊有4Kb存儲(chǔ)，用于數(shù)據(jù)存儲(chǔ)和緩沖，特別適合對(duì)成本敏感和量大的應(yīng)用。本文介紹了iCE40HX系列主要特性，iCE40HX系列架構(gòu)圖，主要產(chǎn)品和特性，以及iCEblink40iCE40HX1K評(píng)估板主要特性，電路圖，主要元件清單和PCB元件布局圖。TheLatticeSemiconductoriCE40LP-SeriesandHX-SeriesprogrammablelogicfamilyaredesignedtodelivertheloweststaticanddynamicpowerconsumptionofanycomparableCPLDorFPGAdevice.iCE40FPGAsaredesignedspecificallyforcost-sensitive，high-volumeapplications.iCE40FPGAarefullyuser-programmableandcanself-configurefromaconfigurationimagestoredinon-chip，nonvolatileconfigurationmemory（NVCM）orstoredinanexternalcommoditySPIserialFlashPROMordownloadedfromanexternalprocessoroveranSPI-likeserialport.iCE40componentsdeliverfromapproximately640to7，680logiccellsandflip-flopswhileconsumingafractionofthepowerofcomparableprogrammablelogicdevices.EachiCE40deviceincludes8to32RAMblocks，eachwith4Kbitsstorage，foron-chipdatastorageanddatabuffering.EachiCE40deviceconsistsoffiveprimaryarchitecturalelements.AnarrayofProgrammableLogicBlocks（PLBs）

EachPLBcontainseightLogicCells（LCs）;eachLogicCellconsistsof…Afast，four-inputlook-uptable（LUT4）capableofimplementinganycombinationallogicfunctionofuptofourinputs，regardlessofcomplexityA‘D’-typeflip-flopwithanoptionalclock-enableandset/resetcontrol

Fastcarrylogicacceleratesarithmeticfunctions：adders，subtracters，comparators，andcounters.Commonclockinputwithpolaritycontrol，clock-enableinput，andoptionalset/resetcontrolinputtothePLBissharedamongalleightLogicCells

Two-port，4KbitRAMblocks（RAM4K）256x16defaultconfiguration;selectabledatawidthusingprogrammablelogicresourcesSimultaneousreadandwriteaccess;idealforFIFOmemoryanddatabufferingapplicationsRAMcontentspre-loadableduringconfiguration

FourI/Obankswithindependentsupplyvoltage，multipleProgrammableInput/Output（PIO）blocks

LVCMOSI/OstandardsandLVDSoutputssupportedinallbanks

I/OBank3supportsadditionalLVDS，andSubLVDSI/OstandardsOneortwoPhase-LockedLoops（PLL）

Verylowpower

ClockmultiplicationanddivisionPhaseshiftinginfixed90°incrementsStaticordynamicphaseshiftingProgrammableinterconnectionsbetweenallprogrammablelogicfunctions

Eightdedicatedlow-skew，high-fanoutclockdistributionnetworksiCE40HX系列主要特性：圖1.iCE40HX系列架構(gòu)圖和特性iCE40HX超低功耗可編程邏輯系列主要產(chǎn)品和特性：TheHX-SeriesoftheiCE40?“LosAngeles”mobileFPGA?familyisidealfortabletapplications.Designersofhandheld，battery-basedconsumerproductshavelongawaitedaprogrammablelogicsolutionthatdeliversdesignflexibilityandfasttime-to-marketbenefitscoupledwithfeaturesthataddresstheirpower，logiccapacity，cost，andsmallformfactorrequirements.Thissolution，previouslyunattainablebyotherFPGAsuppliers，isnowprovidedbyLattice’sultra-lowpowermobileFPGAdevices.UtilizingthemobileFPGAplatform，mobiledesignerscanquicklybringnewfeaturesandcustomfunctionalitytomarketwiththeirveryownCustomMobileDevice.DesignerscanachievethisbyeitherusingstateoftheartdevelopmentsoftwareorbyutilizingLattice’sdesignservices.KeyFeaturesIdealforsensormanagementfunctionsincludinginterruptfiltering，interruptaggregation，autopollingBatteryinsertionandaudioinsertiondetectionwithhighspeedcomparatorsSupportMIPISLIMbusInterfaceHighspeedLVDSchannelsupto525MbpsperchannelHighdefinitionvideosupport：HD720p@60Hz，HD1080p@30HzSupportsMIPIDBIandMIPIDPIvideointerfacestandardsHighSpeedUSB2.0hostanddevicecontrollerssupportingULPIandUTMIinterfacesIdealfor3DsolutionsPCBfriendlyfootprintpackagesFabricatedonadvanced40nmstandardCMOSprocess50%fasterthaniCE65?devicesUltra-lowpowerconsumptionUltra-smallfootprintpackagesWorld’sfirst2.5x2.5mm，0.4mmpitchballgridarray2Xlogiccapacitypermm2overiCE65Upto2phase-lockedloopssupportingdualoutputsFlexibleblockRAMiCEblink40iCE40HX1K評(píng)估板ThisguidedescribeshowtobeginusingtheiCEblink40EvaluationKit，aneasy-to-useplatformforrapidlyprototyp-ingdesignsusingtheiCE40mobileFPGA?。iCEblink40iCE40HX1K評(píng)估板主要特性：?High-performance，low-poweriCE40HX1KmobileFPGA?USBprogramming，debugging，virtualI/Ofunctions，andpowersupply?FouruserLEDs?Fourcapacitive-touchbuttons?3.3MHzclocksource?1MbitSPIserialconfigurationPROM?SupportedbyLatticeiCEcube2?designsoftware?68LVCMOS/LVTTL（3.3V）digitalI/Oconnectionson0.1”th