如何使用Verilog實(shí)現(xiàn)具有預(yù)生成系數(shù)的簡(jiǎn)單FIR濾波器

如何使用Verilog實(shí)現(xiàn)具有預(yù)生成系數(shù)的簡(jiǎn)單FIR濾波器？緒論不起眼的FIR濾波器是FPGA數(shù)字信號(hào)處理中最基本的模塊之一，因此了解如何將具有給定抽頭數(shù)及其相應(yīng)系數(shù)值的基本模塊組合在一起非常重要。因此，在這個(gè)關(guān)于FPGA上DSP基礎(chǔ)實(shí)用入門的教程中，將從一個(gè)簡(jiǎn)單的15抽頭低通濾波器FIR開始，在Matlab中為其生成初始系數(shù)值，然后轉(zhuǎn)換這些值用于編寫Verilog模塊。有限脈沖響應(yīng)或FIR濾波器定義為脈沖響應(yīng)在特定時(shí)間段內(nèi)穩(wěn)定為零值的濾波器。脈沖響應(yīng)穩(wěn)定到零所花費(fèi)的時(shí)間與濾波器階數(shù)（抽頭數(shù)）直接相關(guān)，濾波器階數(shù)是FIR的基礎(chǔ)傳遞函數(shù)多項(xiàng)式的階數(shù)。FIR的傳遞函數(shù)不包含反饋，因此如果輸入一個(gè)值為1的脈沖，然后輸入一串零值，輸出將只是濾波器的系數(shù)值。濾波器的作用基本都是用于信號(hào)調(diào)節(jié)，主要集中在選擇濾除或允許通過哪些頻率。最簡(jiǎn)單的例子之一是低通濾波器，它允許低于某個(gè)閾值（截止頻率）的頻率通過，同時(shí)大大衰減高于該閾值的頻率，如下圖所示。該項(xiàng)目的主要重點(diǎn)是在HDL（具體為Verilog）中實(shí)現(xiàn)FIR，它可以分解為三個(gè)主要邏輯組件：一個(gè)循環(huán)緩沖器，用于將每個(gè)樣本計(jì)時(shí)到適當(dāng)?shù)乜紤]了串行輸入的延遲、每個(gè)抽頭系數(shù)值的乘法器以及每個(gè)抽頭輸出的求和結(jié)果的累加器。由于本項(xiàng)目專注于FPGA邏輯中FIR的設(shè)計(jì)機(jī)制，所以只是使用Simulink中的FDA工具和Matlab為低通濾波器插入一些簡(jiǎn)單參數(shù)，然后使用生成的系數(shù)值放到Verilog模塊中完成濾波器的設(shè)計(jì)（在后面的步驟中完成）。選擇實(shí)現(xiàn)一個(gè)簡(jiǎn)單的15抽頭低通濾波器FIR，采樣率為1Ms/s，通帶頻率為200kHz，阻帶頻率為355kHz，得到以下系數(shù)：-0.026500.04410-0.093400.31390.50000.31390-0.093400.04410-0.0265為FIR模塊創(chuàng)建設(shè)計(jì)文件在Vivado項(xiàng)目中添加源文件。在確定FIR的順序（抽頭數(shù)）并獲得系數(shù)值后，接下來(lái)需要定義的下一組參數(shù)就是輸入樣本、輸出樣本和系數(shù)本身的位寬。對(duì)于這個(gè)FIR，選擇將輸入樣本和系數(shù)寄存器設(shè)置為16位寬，并將輸出樣本寄存器設(shè)置為32位，因?yàn)閮蓚€(gè)16位值的乘積是一個(gè)32位值（兩個(gè)值的寬度相乘得到乘積的寬度，所以如果選擇了8位抽頭的16位輸入樣本，那么輸出樣本將為24位寬）。這些值也都是帶符號(hào)的，因此MSB用作符號(hào)位，在選擇輸入樣本寄存器的初始寬度時(shí)一定要記住這一點(diǎn)。要在Verilog中將這些值設(shè)置為有符號(hào)數(shù)據(jù)類型，使用關(guān)鍵字signed：`regsigned[15:0]register_name;`接下來(lái)要解決的是如何在Verilog中處理系數(shù)值，小數(shù)點(diǎn)值需要轉(zhuǎn)換為定點(diǎn)值。由于所有系數(shù)值都小于1，因此寄存器的所有15位（總共16位，MSB是有符號(hào)位）都可以用于小數(shù)位。通常，必須決定要將寄存器中的多少位用于數(shù)字的整數(shù)部分與數(shù)字的小數(shù)部分。因此，轉(zhuǎn)換分?jǐn)?shù)值抽頭的數(shù)學(xué)是：(fractionalcoefficientvalue)*(2^(15))該乘積的小數(shù)值被四舍五入，并且如果系數(shù)為負(fù)，則計(jì)算該值的二進(jìn)制補(bǔ)碼：`tap0=twos(-0.0265*32768)=0xFC9Ctap1=0tap2=0.0441*32768=1445.0688=1445=0x05A5tap3=0tap4=twos(-0.0934*32768)=0xF40Ctap5=0tap6=0.3139*32768=10285.8752=10285=0x282Dtap7=0.5000*32768=16384=0x4000tap8=0.3139*32768=10285.8752=10285=0x282Dtap9=0tap10=twos(-0.0934*32768)=0xF40Ctap11=0tap12=0.0441*32768=1445.0688=1445=0x05A5tap13=0tap14=twos(-0.0265*32768)=0xFC9C`現(xiàn)在我們終于準(zhǔn)備好關(guān)注FIR模塊的邏輯，第一個(gè)是循環(huán)緩沖區(qū)，它引入串行輸入樣本流并為濾波器的15個(gè)抽頭創(chuàng)建一個(gè)包含15個(gè)輸入樣本的數(shù)組。`always@(posedgeclk)beginif(enable_buff==1'b1)beginbuff0<=in_sample;buff1<=buff0;buff2<=buff1;buff3<=buff2;buff4<=buff3;buff5<=buff4;buff6<=buff5;buff7<=buff6;buff8<=buff7;buff9<=buff8;buff10<=buff9;buff11<=buff10;buff12<=buff11;buff13<=buff12;buff14<=buff13;endend`接下來(lái)，乘法階段將每個(gè)樣本乘以每個(gè)系數(shù)值：`/*MultiplystageofFIR*/always@(posedgeclk)beginif(enable_fir==1'b1)beginacc0<=tap0*buff0;acc1<=tap1*buff1;acc2<=tap2*buff2;acc3<=tap3*buff3;acc4<=tap4*buff4;acc5<=tap5*buff5;acc6<=tap6*buff6;acc7<=tap7*buff7;acc8<=tap8*buff8;acc9<=tap9*buff9;acc10<=tap10*buff10;acc11<=tap11*buff11;acc12<=tap12*buff12;acc13<=tap13*buff13;acc14<=tap14*buff14;endend`乘法階段的結(jié)果值通過加法累加到寄存器中，最終成為濾波器的輸出數(shù)據(jù)流。`/*AccumulatestageofFIR*/always@(posedgeclk)beginif(enable_fir==1'b1)beginm_axis_fir_tdata<=acc0+acc1+acc2+acc3+acc4+acc5+acc6+acc7+acc8+acc9+acc10+acc11+acc12+acc13+acc14;endend`最后，邏輯的最后一部分是將數(shù)據(jù)流進(jìn)和流出FIR模塊的接口。AXIStream接口是最常見的接口之一。關(guān)鍵方面是允許控制上游和下游設(shè)備之間的數(shù)據(jù)流的tready和tvalid信號(hào)。這意味著FIR模塊需要向其下游設(shè)備提供tvalid信號(hào)以指示其輸出是有效數(shù)據(jù)，并且如果下游設(shè)備解除其tready信號(hào)，則能夠暫停（但仍保留）其輸出。FIR模塊還必須能夠與其主端接口上的上游設(shè)備以同樣的方式運(yùn)行。以下是FIR模塊的邏輯設(shè)計(jì)概述：請(qǐng)注意tready和tvalid信號(hào)如何設(shè)置輸入循環(huán)緩沖器的使能值和FIR的乘法級(jí)以及數(shù)據(jù)或系數(shù)通過的每個(gè)寄存器都被聲明為有符號(hào)的。FIR模塊Verilog代碼：```timescale1ns/1psmoduleFIR(inputclk,inputreset,inputsigned[15:0]s_axis_fir_tdata,input[3:0]s_axis_fir_tkeep,inputs_axis_fir_tlast,inputs_axis_fir_tvalid,inputm_axis_fir_tready,outputregm_axis_fir_tvalid,outputregs_axis_fir_tready,outputregm_axis_fir_tlast,outputreg[3:0]m_axis_fir_tkeep,outputregsigned[31:0]m_axis_fir_tdata);always@(posedgeclk)beginm_axis_fir_tkeep<=4'hf;endalways@(posedgeclk)beginif(s_axis_fir_tlast==1'b1)beginm_axis_fir_tlast<=1'b1;endelsebeginm_axis_fir_tlast<=1'b0;endend//15-tapFIRregenable_fir,enable_buff;reg[3:0]buff_cnt;regsigned[15:0]in_sample;regsigned[15:0]buff0,buff1,buff2,buff3,buff4,buff5,buff6,buff7,buff8,buff9,buff10,buff11,buff12,buff13,buff14;wiresigned[15:0]tap0,tap1,tap2,tap3,tap4,tap5,tap6,tap7,tap8,tap9,tap10,tap11,tap12,tap13,tap14;regsigned[31:0]acc0,acc1,acc2,acc3,acc4,acc5,acc6,acc7,acc8,acc9,acc10,acc11,acc12,acc13,acc14;/*TapsforLPFrunning@1MSpswithacutofffreqof400kHz*/assigntap0=16'hFC9C;//twos(-0.0265*32768)=0xFC9Cassigntap1=16'h0000;//0assigntap2=16'h05A5;//0.0441*32768=1445.0688=1445=0x05A5assigntap3=16'h0000;//0assigntap4=16'hF40C;//twos(-0.0934*32768)=0xF40Cassigntap5=16'h0000;//0assigntap6=16'h282D;//0.3139*32768=10285.8752=10285=0x282Dassigntap7=16'h4000;//0.5000*32768=16384=0x4000assigntap8=16'h282D;//0.3139*32768=10285.8752=10285=0x282Dassigntap9=16'h0000;//0assigntap10=16'hF40C;//twos(-0.0934*32768)=0xF40Cassigntap11=16'h0000;//0assigntap12=16'h05A5;//0.0441*32768=1445.0688=1445=0x05A5assigntap13=16'h0000;//0assigntap14=16'hFC9C;//twos(-0.0265*32768)=0xFC9C/*ThisloopsetsthetvalidflagontheoutputoftheFIRhighonce*thecircularbufferhasbeenfilledwithinputsamplesforthe*firsttimeafteraresetcondition.*/always@(posedgeclkornegedgereset)beginif(reset==1'b0)//if(reset==1'b0||tvalid_in==1'b0)beginbuff_cnt<=4'd0;enable_fir<=1'b0;in_sample<=8'd0;endelseif(m_axis_fir_tready==1'b0||s_axis_fir_tvalid==1'b0)beginenable_fir<=1'b0;buff_cnt<=4'd15;in_sample<=in_sample;endelseif(buff_cnt==4'd15)beginbuff_cnt<=4'd0;enable_fir<=1'b1;in_sample<=s_axis_fir_tdata;endelsebeginbuff_cnt<=buff_cnt+1;in_sample<=s_axis_fir_tdata;endendalways@(posedgeclk)beginif(reset==1'b0||m_axis_fir_tready==1'b0||s_axis_fir_tvalid==1'b0)begins_axis_fir_tready<=1'b0;m_axis_fir_tvalid<=1'b0;enable_buff<=1'b0;endelsebegins_axis_fir_tready<=1'b1;m_axis_fir_tvalid<=1'b1;enable_buff<=1'b1;endend/*Circularbufferbringinaserialinputsamplestreamthat*createsanarrayof15inputsamplesforthe15tapsofthefilter.*/always@(posedgeclk)beginif(enable_buff==1'b1)beginbuff0<=in_sample;buff1<=buff0;buff2<=buff1;buff3<=buff2;buff4<=buff3;buff5<=buff4;buff6<=buff5;buff7<=buff6;buff8<=buff7;buff9<=buff8;buff10<=buff9;buff11<=buff10;buff12<=buff11;buff13<=buff12;buff14<=buff13;endelsebeginbuff0<=buff0;buff1<=buff1;buff2<=buff2;buff3<=buff3;buff4<=buff4;buff5<=buff5;buff6<=buff6;buff7<=buff7;buff8<=buff8;buff9<=buff9;buff10<=buff10;buff11<=buff11;buff12<=buff12;buff13<=buff13;buff14<=buff14;endend/*MultiplystageofFIR*/always@(posedgeclk)beginif(enable_fir==1'b1)beginacc0<=tap0*buff0;acc1<=tap1*buff1;acc2<=tap2*buff2;acc3<=tap3*buff3;acc4<=tap4*buff4;acc5<=tap5*buff5;acc6<=tap6*buff6;acc7<=tap7*buff7;acc8<=tap8*buff8;acc9<=tap9*buff9;acc10<=tap10*buff10;acc11<=tap11*buff11;acc12<=tap12*buff12;acc13<=tap13*buff13;acc14<=tap14*buff14;endend/*AccumulatestageofFIR*/always@(posedgeclk)beginif(enable_fir==1'b1)beginm_axis_fir_tdata<=acc0+acc1+acc2+acc3+acc4+acc5+acc6+acc7+acc8+acc9+acc10+acc11+acc12+acc13+acc14;endendendmodule``創(chuàng)建仿真文件要測(cè)試FIR模塊，需要?jiǎng)?chuàng)建一個(gè)測(cè)試平臺(tái)作為其仿真源：在FIR模塊中有兩個(gè)主要的東西需要測(cè)試：濾波器算法和AXI流接口。為實(shí)現(xiàn)這一點(diǎn)，測(cè)試臺(tái)中創(chuàng)建了一個(gè)狀態(tài)機(jī)，它生成一個(gè)簡(jiǎn)單的200kHz正弦波，并切換從屬端的有效信號(hào)和FIR接口主控端的tready信號(hào)。FIR模塊的測(cè)試平臺(tái)：```timescale1ns/1psmoduletb_FIR;regclk,reset,s_axis_fir_tvalid,m_axis_fir_tready;regsigned[15:0]s_axis_fir_tdata;wirem_axis_fir_tvalid;wire[3:0]m_axis_fir_tkeep;wire[31:0]m_axis_fir_tdata;/**100Mhz(10ns)clock*/alwaysbeginclk=1;#5;clk=0;#5;endalwaysbeginreset=1;#20;reset=0;#50;reset=1;#1000000;endalwaysbegins_axis_fir_tvalid=0;#100;s_axis_fir_tvalid=1;#1000;s_axis_fir_tvalid=0;#50;s_axis_fir_tvalid=1;#998920;endalwaysbeginm_axis_fir_tready=1;#1500;m_axis_fir_tready=0;#100;m_axis_fir_tready=1;#998400;end/*InstantiateFIRmoduletotest.*/FIRFIR_i(.clk(clk),.reset(reset),.s_axis_fir_tdata(s_axis_fir_tdata),.s_axis_fir_tkeep(s_axis_fir_tkeep),.s_axis_fir_tlast(s_axis_fir_tlast),.s_axis_fir_tvalid(s_axis_fir_tvalid),.m_axis_fir_tready(m_axis_fir_tready),.m_axis_fir_tvalid(m_axis_fir_tvalid),.s_axis_fir_tready(s_axis_fir_tready),.m_axis_fir_tlast(m_axis_fir_tlast),.m_axis_fir_tkeep(m_axis_fir_tkeep),.m_axis_fir_tdata(m_axis_fir_tdata));reg[4:0]state_reg;reg[3:0]cntr;parameterwvfm_period=4'd4;parameterinit=5'd0;parametersendSample0=5'd1;parametersendSample1=5'd2;parametersendSample2=5'd3;parametersendSample3=5'd4;parametersendSample4=5'd5;parametersendSample5=5'd6;parametersendSample6=5'd7;parametersendSample7=5'd8;/*Thisstatemachinegeneratesa200kHzsinusoid.*/always@(posedgeclkorposedgereset)beginif(reset==1'b0)begincntr<=4'd0;s_axis_fir_tdata<=16'd0;state_reg<=init;endelsebegincase(state_reg)init://0begincntr<=4'd0;s_axis_fir_tdata<=16'h0000;state_reg<=sendSample0;endsendSample0://1begins_axis_fir_tdata<=16'h0000;if(cntr==wvfm_period)begincntr<=4'd0;state_reg<=sendSample1;endelsebegincntr<=cntr+1;state_reg<=sendSample0;endendsendSample1://2begins_axis_fir_tdata<=16'h5A7E;if(cntr==wvfm_period)begincntr<=4'd0;state_reg<=sendSample2;endelsebegincntr<=cntr+1;state_reg<=sendSample1;endendsendSample2://3begins_axis_fir_tdata<=16'h7FFF;if(cntr==wvfm_period)begincntr<=4'd0;state_reg<=sendSample3;endelsebegincntr<=cntr+1;state_reg<=sendSample2;endendsendSample3://4begins_axis_fir_tdata<=16'h5A7E;if(cntr==wvfm_period)begincntr<=4'd0;state_reg<=sendSample4;endelsebegincntr<=cntr+1;state_reg<=sendSample3;endendsendSample4://5begins_axis_fir_tdata<=16'h0000;if(cntr==wvfm_period)begincntr<=4'd0;state_reg<=sendSample5;endelsebegincntr<=cntr+1;state_reg<=sendSample4;endendsendSample5://6begins_axis_fir_tdata<=16'hA582;if(cntr==wvfm_period)begincntr<=4'd0;state_reg<=sendSample6;end