數(shù)字電路與邏輯設(shè)計 課件 12-數(shù)字系統(tǒng)設(shè)計-簡易處理器設(shè)計

數(shù)字系統(tǒng)設(shè)計

--簡易處理器設(shè)計片上微控制系統(tǒng)原理與項目設(shè)計第十二講授課內(nèi)容數(shù)字系統(tǒng)設(shè)計處理數(shù)字濾波器控制微處理器設(shè)計處理器電路，計算N！3IntroductionProgrammable(general-purpose)processorMass-produced,thenprogrammedtoimplementdifferentprocessingtasksWell-knowncommonprogrammableprocessors:Pentium,Sun’sSpareOtherprogrammableprocessors:ARM,MIPS,8051,PIC,PowerPCLow-costembeddedprocessorsfoundincellphones,blinkingshoes,etc.HowtodesignasimpleprogrammableprocessorusingdigitaldesignmethodsRealprocessorscanbemuchmorecomplex8.1Seatbeltwarninglightsingle-purposeprocessor2x4e2310c0c1c2xt1regxt0xt2++***x(t)x(t-1)x(t-2)InstructionmemoryControllerPCIRRegisterfileRFDatamemoryDALUn-bit2x1Therepresentationoftheprocessingtaskinthememoryisknownasaprogram3-tapFIRfiltersingle-purposeprocessorGeneral-purposeprocessoraControlunitDatapath4BasicArchitectureProgrammableprocessorconsistsoftwomainparts:AdatapathAcontrolunitProcessinggenerallyconsistsof:LoadingsomedataTransformingthatdataTransformationstakeplaceinsideaprocessor’sdatapath.StoringthatdataBasicdatapath:UsefulcircuitinaprogrammableprocessorCanread/writedatamemory,wheremaindataexistsHasregisterfiletoholddatalocallyHasALUtotransformlocaldata8.2RegisterfileRFDatamemoryDALUn-bit2x1BasicDatapath5BasicDatapathOperationsLoadoperation:LoaddatafromanylocationinthedatamemoryintoanyregisterintheRFALUoperation:TransformsdatabypassingoneortwoRFregistervaluesthroughALU,performingoperation(ADD,SUB,AND,OR,etc.),andwritingbackintoRF.

Storeoperation:Stores(writes)RFregistervaluebackintoanydatamemorylocationNote:EachoperationcanbedoneinoneclockcycleRegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1LoadoperationALUoperationStoreoperationa6UnderstandingDatapathOperationsQ:

Whichofthefollowingarevalidsingle-clock-cycleoperations

forgivendatapath?1.Copydatafromadatamemorylocationintoaregisterfilelocation.A:

YES–That'saloadoperation2.Readdatafromtwodatamemorylocationsintotworegisterfilelocations.A:

NO–readingmorethanonedatamemorylocationandwritingtomorethanoneregisterfilelocationarenotsupportedduringadatapathoperation.3.Adddatafromtwodatamemorylocationsandstoretheresultinaregisterfilelocation.A:

NO –Doesnotsupportreadingtwodatamemorylocationsduringanoperation –Doesnothaveconnectionsdirectlyfromthedatamemory4.Copydatafromoneregisterfilelocationtoanotherregisterfilelocation.A:

YES–Why?5.Subtractdatainaregisterfilelocationfromadatamemorylocation,storingtheresultinaregisterfilelocation.A:

NO–Valuesreadfromdatamemorymustbeloadedintotheregisterfilefirst.a7BasicDatapathOperationsQ:Whicharevalidsingle-cycleoperations

forgivendatapath?MoveD[1]toRF[1](i.e.,RF[1]=D[1])A:YES–That'saloadoperationStoreRF[1]toD[9]andstoreRF[2]toD[10]A:NO–RequirestwoseparatestoreoperationsAddD[0]plusD[1],storeresultinD[9]A:NO–ALUoperation(ADD)onlyworkswithRF.Requirestwoloadoperations(e.g.,RF[0]=D[0];RF[1]=D[1],anALUoperation(e.g.,RF[2]=RF[0]+RF[1]),andastoreoperation(e.g.,D[9]=RF[2])RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1LoadoperationALUoperationStoreoperationaQ&A89BasicArchitecture–ControlUnitSupposethebasicdatapathshouldperformthesimpleprocessingtaskofaddingdatamemorylocation0anddatamemorylocation1together,andwritingtheresultindatamemorylocation9.ComputingD[9]=D[0]+D[1]Thisprocessingtaskcanbeachievedby“instructing”thedatapathtoperformthefollowingoperations:Loaddatapathmemorylocation0toregisterRF[0](i.e.,RF[0]=D[0])Loaddatapathmemorylocation1toregisterRF[1](i.e.,RF[1]=D[1])PerformanALUoperationthataddsRF[0]andRF[1]andwritestheresultbackintoRF[2](i.e.,RF[2]=RF[0]+RF[1])StoreRF[2]intodatamemorylocation9(i.e.,D[9]=RF[2]).D[9]=D[0]+D[1]–requiresasequenceoffourdatapathoperations:0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]a10BasicArchitecture–ControlUnitD[9]=D[0]+D[1]–requiresasequenceoffourdatapathoperations:0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]Eachoperationisaninstruction

Sequenceofinstructions–programLookscumbersome,butthat'stheworldofprogrammableprocessors–Decomposingdesiredcomputationsintoprocessor-supportedoperationsStoreprograminInstructionmemoryControlunitreadseachinstructionandexecutesitonthedatapathPC(Programcounter)–addressofcurrentinstructionIR(Instructionregister)–currentinstructionRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]asignalstocontrolthedatapath11BasicArchitecture–ControlUnitTocarryout

eachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapathaRF[0]=D[0]0->1R[0]:??

99"load"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[0]=D[0]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]1(b)ControllerDecodeRegisterfileRFDatamemoryDD[0]:99ALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[0]=D[0]1(c)Executesignalstocontrolthedatapath12BasicArchitecture–ControlUnitaRF[1]=D[1}1->2R[1]:??

102"load"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[1]=D[1]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]2(b)ControllerDecodeRegisterfileRFDatamemoryDD[1]:102ALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[1]=D[1]2(c)ExecutesignalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath13BasicArchitecture–ControlUnitaRF[2]=RF[0]+RF[1]2->3R[2]:??

201"ALU(add)"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[2]=RF[0]+RF[1]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]3(b)ControllerDecodeRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[2]=RF[0]+RF[1]3(c)Execute99102201signalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath14BasicArchitecture–ControlUnitaD[9]=RF[2]3->4R[2]:201"store"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchD[9]=RF[2]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]4(b)ControllerDecodeRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]D[9]=RF[2]4(c)ExecuteD[9]=??201signalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath15BasicArchitecture–ControlUnitRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]signalstocontrolthedatapathControllerFSM16Example:CreatingaSimpleSequenceofInstructionsQ:Createasetofinstructions(orsequence)tocomputeD[3]=D[0]+D[1]+D[2]onearlier-introducedprocessor.A1:OnepossiblesequenceFirstloaddatamemorylocationsintoregisterfileR[3]=D[0]R[4]=D[1]R[2]=D[2](Notearbitraryregisterlocations)Next,performtheadditionsR[1]=R[3]+R[4]R[1]=R[1]+R[2]Finally,storeresultD[3]=R[1]aA2:AlternativesequenceFirstloadD[0]andD[1]andaddthemR[1]=D[0]R[2]=D[1]R[1]=R[1]+R[2]Next,loadD[2]andaddR[2]=D[2]R[1]=R[1]+R[2]aFinally,storeresultD[3]=R[1]Sixinstructionswouldappearininstructionmemorylocations0through517Example:EvaluatingtheNumberofCyclestoExecuteaProgramQ:Howmanycyclesareneededtoexecutesixinstructionsusingtheearlier-describedprocessor?A:Eachinstructionrequires3cycles:1cycletofetchtheinstruction,1cycletodecodethefetchedinstruction,and1toexecutetheinstruction.At3cyclesperinstruction,thetotalcyclesfor6instructionsis6instr*3cycles/instr=18cyclesaThree-InstructionProgrammableProcessorInstructionSet–ListofallowableinstructionsandtheirrepresentationinmemoryReserveacertainnumberofbitsintheinstructiontodenotewhatoperationtoperformRemainingbitsspecifyadditionalinformationneededtoperformtheoperationsuchastheaddressesoftheregistersthatareinvolvedintheoperationThree16bitswideinstructions,leftmost4bitsidentifytheoperation,andtheremaining12bitsidentifytheregisterfileanddatamemoryaddresses:8.3bit11bit10bit9bit8bit7bit6bit5bit4bit3bit2bit1bit0Operationcode0000:Load0001:Store0010:AddAdditionalinformationbit15bit14bit13bit12Three-InstructionProgrammableProcessorThree16bitswideinstructions,e.g.,Loadinstruction —0000r3r2r1r0

d7d6d5d4d3d2d1d0Storeinstruction —0001r3r2r1r0d7d6d5d4d3d2d1d0Addinstruction —0010ra3ra2ra1ra0

rb3rb2rb1rb0rc3rc2rc1rc0198.3InstructionmemoryI0:00000000000000001:00000001000000012:00100010000000013:00010010000010010:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2}DesiredprogramaopcodeoperandsInstructionsin0sand1s–machinecodeaExample:ProgramforThree-InstructionProcessor20RegisterfileRFDatamemoryDALUn-bit2×1DatapathInstructionmemoryIControlunitControllerPCIRsignalstocontrolthedatapath0:00000000000000001:00000001000000012:00100010000000013:00010010000010010:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2}DesiredprogramComputesD[9]=D[0]+D[1]ThedesiredcomputationD[9]=D[0]+D[1]canbewrittenastheprogram:Example:ProgramforThree-InstructionProcessorWriteprogramstoperformthecomputationD[5]=D[5]+D[6]+D[7]usingtheabove-definedthreeinstructionset.21Loadinstruction—0000r3r2r1r0d7d6d5d4d3d2d1d0Storeinstruction—0001r3r2r1r0d7d6d5d4d3d2d1d0Addinstruction—0010ra3ra2ra1ra0rb3rb2rb1rb0rc3rc2rc1rc0Thenumberbeforethecolonrepresentstheinstruction’saddressintheinstructionmemory.Thetextfollowingthetwoforwardslashes“//”representsacomment,andisnotpartofaninstruction.MachineCodevs.AssemblyCodeAprogramrepresentedas0sand1sisknownasmachinecode.Wehumansarenotgoodatwritingandreadingprogramsas0sand1sCan’tunderstandthose0sand1seasilyWillmakeplentyofmistakeswhenwritingsuchprogramsThus,earlycomputerprogrammersdevelopedatoolknownasanassembler(whichitselfisjustanotherprogram)tohelphumanswriteprograms.Allowsustowriteinstructionsusingmnemonics(助記符),orsymbolsAssemblerautomaticallytranslatestomachinecode22AssemblyCodeMachinecode(0sand1s)hardtoworkwithAssemblycode–Usesmnemonics(助記符)Loadinstruction—MOVRa,dspecifiestheoperationRF[a]=D[d].amustbe0,1,...,or15—soR0meansRF[0],R1meansRF[1],etc.dmustbe0,1,...,255?Storeinstruction—MOVd,RaspecifiestheoperationD[d]=RF[a]?Addinstruction—ADDRa,Rb,RcspecifiestheoperationRF[a]=RF[b]+RF[c]230:MOVR0,01:MOVR1,12:ADDR2,R0,R13:MOV9,R20:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]Desiredprogram0:00000000000000001:00000001000000012:00100010000000013:0001001000001001machinecodeassemblycodeTheprogramwrittenusingmnemonicsismucheasiertounderstandthanthe0sand1s,andthatwillbetranslatedtomachinecodebyanassembler(assemblycode).Control-UnitandDatapathforThree-InstructionProcessorTodesignacompletedigitalcircuitforathree-instructionprogrammableprocessor,wecanbeginwithahigh-levelstatemachinedescriptionoftheprocessor'sbehavior24StoreD[d]=RF[ra]op=0001LoadRF[ra]=D[d]op=0000DecodeFetchIR=I[PC]PC=PC+1InitPC=0AddRF[ra]=RF[rb]+RF[rc]op=0010opmeansIR[15..12]rameansIR[11..8]rbmeansIR[7..4]rcmeansIR[3..0]dmeansIR[7..0]executestates簡易處理器設(shè)計Control-UnitandDatapathforThree-InstructionProcessorCreatedetailedconnectionsamongcomponents26FetchDecodeInitPC=0StoreIR=I[PC]PC=PC+1LoadAddRF[ra]=RF[rb]+RF[rc]D[d]=RF[ra]RF[ra]=D[d]op=0000op=0001op=0010PCclrup16I_rdPC_incIRId1616R_ldIdatardaddrControllerControlunitDatapathRF_W_wrRF_Rp_addrRF_Rq_addrRF_Rq_rdRF_Rp_rdRF_W_addrD_addr8D_rdD_wrRF_salu_s0addrDrdwr256x1616x16RF16-bit2x1W_dataR_dataRp_dataRq_dataW_dataW_addrW_wrRp_addrRp_rdRq_addrRq_rd0161616161616s1ABs0ALU444PC_clrAssumethat:alu_s0=1,ALUaddsitsinputsalu_s0=0,ALUpassesinputARF_sistheselectlineforthe2x1muxDatamemoryRefineddatapathandcontrolunitforthethree-instructionprocessorInstructionmemoryControl-UnitandDatapathforThree-InstructionProcessorConverthigh-levelstatemachinedescriptionofentireprocessortoFSMdescriptionofcontrollerthatusesdatapathandothercomponentstoachievesamebehavior27FetchDecodeInitPC=0PC_clr=1StoreIR=I[PC]PC=PC+1I_rd=1PC_inc=1IR_ld=1LoadAddRF[ra]=RF[rb]+RF[rc]D[d]=RF[ra]RF[ra]=D[d]op=0000op=0001op=0010D_addr=dD_wr=1RF_s=XRF_Rp_addr=raRF_Rp_rd=1RF_Rp_addr=rbRF_Rp_rd=1RF_s=0RF_Rq_addr=rcRF_Rq_rd=1RF_W_addr=raRF_W_wr=1alu_s0=1D_addr=dD_rd=1RF_s=1RF_W_addr=raRF_W_wr=1aASix-InstructionProgrammableProcessorLet'saddthreemoreinstructions:Load-constantinstruction—0011r3r2r1r0c7c6c5c4c3c2c1c0MOVRa,#c—specifiestheoperationRF[a]=cSubtractinstruction—0100ra3ra2ra1ra0rb3rb2rb1rb0rc3rc2rc1rc0SUBRa,Rb,Rc—specifiestheoperationRF[a]=RF[b]–RF[c]Jump-if-zeroinstruction—0101ra3ra2ra1ra0o7o6o5o4o3o2o1o0JMPZRa,offset—specifiestheoperationPC=PC+offsetifRF[a]is0288.4ExtendingtheControl-UnitandDatapath291:TheloadconstantinstructionrequiresthattheregisterfilebeabletoloaddatafromIR[7..0],inadditiontodatafromdatamemoryortheALUoutput.Thus,wewidentheregisterfile’smultiplexerfrom2x1to3x1,addanothermuxcontrolsignal,andalsocreateanewsignalcomingfromthecontrollerlabeledRF_W_data,whichwillconnectwithIR[7..0].(shownaslabeled1)2:ThesubtractinstructionrequiresthatweuseanALUcapableofsubtraction,soweaddanotherALUcontrolsignal.(shownaslabeled2)3:Thejump-if-zeroinstructionrequiresthatwebeabletodetectifaregisteriszero,andthatwebeabletoaddIR[7..0]tothePC. 3a:Weinsertadatapathcomponenttodetectiftheregisterfile’sRpreadportisallzeros(thatcomponentwouldjustbeaNORgate).(shownaslabeled3a) 3b:WealsoupgradethePCregistersoitcanbeloadedwithPCplusIR[7..0].Theadderusedforthisalsosubtracts1fromthesum,tocompensateforthefactthattheFetchstatealreadyadded1tothePC.(shownaslabeled3b)DatapathRF_Rp_addrRF_Rq_addrRF_Rp_zeroRF_W_addrD_addrD_rdD_wrRF_s1RF_W_dataRF_s0alu_s1alu_s0addrDrdwr256x1616x16RF16-bit3x1W_dataR_dataRp_dataRq_dataW_dataW_addrW_wrRp_addrRp_rdRq_addrRq_rd0161616161616s1s012ABs1s0ALU4443a2=01188s1001s0010ALUoperationpassAthroughA+BA-BPCclrldup16IRId16datardaddrControllerControlunita+b-116**+3bIR[7..0]RF_W_wrRF_Rp_rdRF_Rq_rdExample:ProgramfortheSix-InstructionProcessorExampleprogram–Countnumberofnon-zerowordsinD[4]andD[5]Resultwillbeeither0,1,or2PutresultinD[9]30AssemblycodeCorrespondingmachinecodegeneratedbyanassemblerNote:Thespacesinthemachinecode’s16-bitinstructionsarethereforeaseofreadingbyus,actualmachinecodehasnosuchspaces.FurtherExtensionstotheProgrammableProcessorTypicalprocessorinstructionsetwillcontaindozensofdatamovement(e.g.,loads,stores),ALU(e.g.,add,sub),andflow-of-control(e.g.,jump)instructionsExtendingthecontrol-unit/datapathfollowssimilarlytopreviously-shownextensionsInput/outputextensionsCertainmemorylocationsmayactuallybeexternalpinse.g,D[240]mayrepresent8-bitinputI0,D[255]mayrepresent8-bitoutputP7318.5256x16DW_dataR_dataaddrrdwr0:1:2:239:240:241:248:255:00..000..0I0I1P0P7ProgramusingI/OExtensionsMicroprocessorsacommonchoicetoimplementadigitalsystemEasytoprogramCheap(aslowas$1)Availablenow32I3I4I5I6I7I2I1I0P3P4P5P6P7P2P1P0voidmain(){while(1){P0=I0&&!I1;//F=aand!b,}}0Fba101016:007:057:069:009:01timeDesiredmotion-at-nightdetectorProgrammedmicroprocessorCustomdesigneddigitalcircuitProgramUsingInput/OutputExtensionsUnderlyingassemblycodeforCexpressionI0&&!I1.330:MOVR0,240//moveD[240],whichisthevalueatpinI0,intoR01:MOVR1,241//moveD[241],whichisthatvalueatpinI1,intoR12:NOTR1,R1//compute!I1,assumingexistenceofacomplementinstruction3:ANDR0,R0,R1//computeI0&&!I1,assuminganANDinstruction4:MOV248,R0//moveresulttoD[248],whichispinP0256x16DW_dataR_dataaddrrdwr0:1:2:239:240:241:248:255:00..000..0I0I1P0P7voidmain(){while(1){P0=I0&&!I1;//F=aand!b,}}控制器設(shè)計思路控制器主要模塊時序控制模塊取指處理模塊指令譯碼模塊控制指令設(shè)計思路--時序控制每條指令的執(zhí)行需要控制單元協(xié)調(diào)多個電路按照規(guī)程進(jìn)行工作，每個電路所需要的控制信號需要在不同時間內(nèi)生效。幾種參考流程設(shè)計自己的控制流程控制指令設(shè)計思路--時序控制實現(xiàn)將一次操作采用三個時鐘周期完成。第0個時鐘上升沿鎖存PC，第1個時鐘內(nèi)完成譯指、取數(shù)和運算，第2個時鐘完成存儲器讀或?qū)懸约拜敵黾拇嫫麈i存使能。在第3個時鐘到來時，進(jìn)行新一輪指令操作。電路主要信號的時序圖時序控制模塊還可以將譯碼的控制結(jié)果在指定時鐘輸出。

CLKmLEmWRmRDmLEmSLEnWRnRDLESLEPCLE功能↑0xxxx-----保持↑10xxx01001PC

PC+1↑110xx10001

↑1xx0x--101

↑1xxx0--011

PCLE：PC鎖存使能LE：通用寄存器Rx鎖存使能SLE：PSR鎖存使能，nRD：輸出存儲器讀取nWR：輸出存儲器載入parameterSI=2'b00,S0=2'b01,S1=2'b10,S2=2'b11;reg[1:0]state=SI;reg[1:0]next_state=S0;

always@(negedgeclk)begin//Thisisacombinationalalwaysblock//if(state==SI)//begin

//endcase(state)SI:next_state=2'b01;S0:next_state=S1;