數(shù)字電路與邏輯設計 課件 （陳彥輝）11-13 數(shù)字系統(tǒng)設計

數(shù)字系統(tǒng)設計 1

片上微控制系統(tǒng)原理與項目設計第十一講授課內(nèi)容數(shù)字系統(tǒng)設計處理數(shù)字濾波器控制微處理器設計電路，計算N！數(shù)字系統(tǒng)設計核心是自頂向下的設計思想和模塊化的設計方法：（1）模塊劃分，即系統(tǒng)應該被劃分為幾個模塊；（2）模塊互聯(lián)，即各個模塊間的連接接口如何規(guī)劃；（3）模塊通信，即各個模塊之間的數(shù)據(jù)如何交互。（1）試湊法把系統(tǒng)的總體方案分成若干個相對獨立的功能部件，然后用組合邏輯電路和時序邏輯電路的設計方法分別設計并構(gòu)成這些功能部件，最后把這些已經(jīng)確定的部件按要求拼接組合起來，便構(gòu)成完整的數(shù)字系統(tǒng)。（2）自上而下法把較大規(guī)模的數(shù)字系統(tǒng)從邏輯上劃分為控制器和受控制器電路兩大部分，采用邏輯流程圖或其他工具來描述控制器的控制過程，并根據(jù)控制器及受控制器的邏輯功能，選擇適當功能器件來實現(xiàn)。某簡單的小型數(shù)字系統(tǒng)的功能要求如下：有4×4矩陣數(shù)字鍵盤和一行5個數(shù)碼管。每個按鍵上標有一位十六進制數(shù)符，十六個按鍵標注不同值。每按一次鍵，相應的十六進制數(shù)符就顯示在最右邊的數(shù)碼管上，以前顯示的數(shù)符都向左移一個數(shù)碼管。需求可以分解為三個基本子功能部分：數(shù)碼管的動態(tài)顯示矩陣鍵盤的按鍵檢測數(shù)據(jù)移位保存數(shù)據(jù)處理基本模塊輸入輸出邏輯結(jié)構(gòu)功能描述真值表硬件描述波形圖電路內(nèi)部結(jié)構(gòu)加工流程流程描述處理流程圖流程變形按照模塊功能改變流程圖流程結(jié)構(gòu)根據(jù)流程圖用模塊構(gòu)建獲取加工顯示數(shù)據(jù)處理運算流控算術(shù)邏輯比較編碼譯碼變換選擇分配保存寄存存儲運算模塊算術(shù)運算

ABF邏輯運算

AF

比較運算

ABSA>BSA=BSA<B雙目運算單目運算變換模塊編碼

I0IN-1譯碼D……

Y0YN-1D……M<<N壓縮去壓縮N維稀疏空間M維稠密空間N維稀疏空間第幾種情況流控模塊選擇

D0DN-1分配YC……

Y0YN-1D……選來源選去處Cif(C==0)Y=D0;elseif(C==1)Y=D1;elseif()

?elseY=DN-1;if(C==0){Y0=D;Y1=×;…;YN-1=×;}elseif(C==1)){Y0=×;Y1=D;…;YN-1=×;}elseif()

?else{Y0=×;Y1=×;…;YN-1=D;}保存模塊寄存

D存儲Q

A0AN-1WR……不觸發(fā)時保持原值存數(shù)據(jù)CPD0DM-1…RD取數(shù)據(jù)地址線入數(shù)據(jù)線寫使能讀使能…讀寫同時讀寫分時一組數(shù)據(jù)大量數(shù)據(jù)s=f(s,…);x[k]=;=f(x[k],…)A0AN-1WR……DI0DIM-1…RD…DO0DOM-1……出數(shù)據(jù)線雙向數(shù)據(jù)線讀寫同時流程分析

ABFABFABF123N…si=2s=1i>Ns=s+ii=i+1假初始化

ΣΣΣ保存i保存s比較循環(huán)體節(jié)奏時鐘觸發(fā)真流程變形

i=2s=1i>Ns=s+ii=i+1假i=2s=1i>Ns=s+ii=i+1真s=si=i假條件不成立時，s和i值保持原值真要做的操作一直存在，只是是否使用流程變形

初始化與循環(huán)時，s和i值賦值不同i=2s=1i>Ns=s+ii=i+1真s=si=i假s=1i=2i>Ns=s+ii=i+1假s=si=i真初始否真假不同條件下選擇不同結(jié)果所有操作都在流程邏輯結(jié)構(gòu)s=1i=2i>Ns=s+ii=i+1假s=si=i真初始否假真

初始控制節(jié)奏控制輸入?yún)?shù)DQCPABΣF1iDQCPsD0D1YCABΣFD0D1YCABSA<BND1D0YCD1D0YC21CPR流程邏輯結(jié)構(gòu)DQCPABΣF1iDQCPsD0D1YCABΣFD0D1YCABSA<BND1D0YCD1D0YC21CPRds=1di=2i>Nds=s+idi=i+1s=dsi=di假ds=sdi=i真初始否假真

dsdi組合邏輯記憶時序邏輯數(shù)字系統(tǒng)RTL設計方法1、系統(tǒng)狀態(tài)轉(zhuǎn)移圖描述。（與普通的狀態(tài)轉(zhuǎn)移圖相比，轉(zhuǎn)移條件不僅僅是某些輸入輸出比特）2、設計數(shù)據(jù)通路3、將數(shù)據(jù)通路與一個控制器相連4、將系統(tǒng)狀態(tài)轉(zhuǎn)移圖描述轉(zhuǎn)換為模塊狀態(tài)轉(zhuǎn)移圖。（把操作換成控制信號的輸出。）（2）自上而下法把較大規(guī)模的數(shù)字系統(tǒng)從邏輯上劃分為控制器和受控制器電路兩大部分，采用邏輯流程圖或其他工具來描述控制器的控制過程，并根據(jù)控制器及受控制器的邏輯功能，選擇適當功能器件來實現(xiàn)。【例】飲料販賣機。輸入硬幣，c檢測信號，是否有硬幣投入。a為投入錢幣面值信息:1元面值。每瓶飲料的價格s為2元，得控制輸出，控制飲料掉落。①系統(tǒng)狀態(tài)圖定義變量tot，累計現(xiàn)有錢數(shù)?初始化狀態(tài)：設置d=0，tot=0?等待狀態(tài)：等待硬幣 –如果看到硬幣，請轉(zhuǎn)到添加狀態(tài)?添加狀態(tài)：更新總值：tot=tot

+a –存儲當前硬幣的價值，返回等待狀態(tài) –在等待狀態(tài)下，如果tot>=s，請轉(zhuǎn)到分配?分配狀態(tài)：設置d=1（分配飲料） –返回初始化狀態(tài)多位（數(shù)據(jù)）輸入a和s本地注冊數(shù)據(jù)操作tot=0，tot<s，tot=tot+a。

設計數(shù)據(jù)通路需要寄存器tot需要8位比較器比較S和TOT需要8位加法器執(zhí)行tot=tot+a連接各模快控制輸入/輸出，定義信號名稱

將數(shù)據(jù)通路與一個控制器相連控制器的輸入 –外部輸入c

（檢測到硬幣） –來自數(shù)據(jù)路徑的輸入

比較器輸出，命名的tot_lt_s?控制器輸出 –外部輸出d（分配飲料） –控制輸出tot_ld,tot_clr

轉(zhuǎn)換為模塊狀態(tài)轉(zhuǎn)移圖

狀態(tài)和轉(zhuǎn)移不變

讀寫控制單元信號【例】基于激光的距離測量儀輸入輸出：B控制開關(guān)L激活激光S激光接收器D16比特距離數(shù)據(jù)創(chuàng)建初始狀態(tài)，將其命名為S0–將激光初始化為關(guān)閉（L=0）–將顯示的距離初始化為0（D=0）添加另一個狀態(tài)，稱為S1，等待按鈕按下–B'–留在S1，繼續(xù)等待–B–轉(zhuǎn)到新狀態(tài)S2問：S2應該做什幺？答：打開激光添加打開激光的狀態(tài)S2（L=1）在狀態(tài)S3中關(guān)閉激光（L=0）問：下一步做什幺？答：啟動定時器，等待反射檢測到反射（S）后，進入新狀態(tài)S4–計算距離–假設時鐘頻率為3x108，DCTR保存米數(shù)，因此D=DCTR/2?S4之后，返回S1再次等待按鈕2、設計數(shù)據(jù)通路數(shù)據(jù)通路數(shù)據(jù)存儲數(shù)據(jù)計算看系統(tǒng)狀態(tài)機，三個子步驟（a）使數(shù)據(jù)輸入/輸出成為數(shù)據(jù)路徑輸入/輸出（b）將聲明的寄存器實例化到數(shù)據(jù)路徑（同時為每個實例化一個寄存器數(shù)據(jù)輸出）（c）審查每一種狀態(tài)和轉(zhuǎn)移，以及實例化數(shù)據(jù)路徑模塊和用于實現(xiàn)任何數(shù)據(jù)的計算【例】總線接口–主處理器可以讀取任何外設寄存器 ?每個寄存器都有唯一的4位地址 ?假設1個寄存器/外設。–設置rd=1，A=地址–在32位D線上寄存器數(shù)據(jù) ?硬件地址Faddr輸入（可能來自DIP開關(guān)或他寄存器）步驟1：創(chuàng)建高級狀態(tài)機–狀態(tài)等待?在D上輸出“無”（“Z”），將外設的寄存器值Q存儲到本地寄存器Q1?等到看到此外設的地址（A=Faddr）且rd=1–狀態(tài)發(fā)送數(shù)據(jù)?將Q1輸出到D上，等待rd=0（表示主處理器已完成讀取D）【例】視頻壓縮【例】數(shù)字濾波器數(shù)字系統(tǒng)設計

--簡易處理器設計片上微控制系統(tǒng)原理與項目設計第十二講授課內(nèi)容數(shù)字系統(tǒng)設計處理數(shù)字濾波器控制微處理器設計處理器電路，計算N！55IntroductionProgrammable(general-purpose)processorMass-produced,thenprogrammedtoimplementdifferentprocessingtasksWell-knowncommonprogrammableprocessors:Pentium,Sun’sSpareOtherprogrammableprocessors:ARM,MIPS,8051,PIC,PowerPCLow-costembeddedprocessorsfoundincellphones,blinkingshoes,etc.HowtodesignasimpleprogrammableprocessorusingdigitaldesignmethodsRealprocessorscanbemuchmorecomplex8.1Seatbeltwarninglightsingle-purposeprocessor2x4e2310c0c1c2xt1regxt0xt2++***x(t)x(t-1)x(t-2)InstructionmemoryControllerPCIRRegisterfileRFDatamemoryDALUn-bit2x1Therepresentationoftheprocessingtaskinthememoryisknownasaprogram3-tapFIRfiltersingle-purposeprocessorGeneral-purposeprocessoraControlunitDatapath56BasicArchitectureProgrammableprocessorconsistsoftwomainparts:AdatapathAcontrolunitProcessinggenerallyconsistsof:LoadingsomedataTransformingthatdataTransformationstakeplaceinsideaprocessor’sdatapath.StoringthatdataBasicdatapath:UsefulcircuitinaprogrammableprocessorCanread/writedatamemory,wheremaindataexistsHasregisterfiletoholddatalocallyHasALUtotransformlocaldata8.2RegisterfileRFDatamemoryDALUn-bit2x1BasicDatapath57BasicDatapathOperationsLoadoperation:LoaddatafromanylocationinthedatamemoryintoanyregisterintheRFALUoperation:TransformsdatabypassingoneortwoRFregistervaluesthroughALU,performingoperation(ADD,SUB,AND,OR,etc.),andwritingbackintoRF.

Storeoperation:Stores(writes)RFregistervaluebackintoanydatamemorylocationNote:EachoperationcanbedoneinoneclockcycleRegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1LoadoperationALUoperationStoreoperationa58UnderstandingDatapathOperationsQ:

Whichofthefollowingarevalidsingle-clock-cycleoperations

forgivendatapath?1.Copydatafromadatamemorylocationintoaregisterfilelocation.A:

YES–That'saloadoperation2.Readdatafromtwodatamemorylocationsintotworegisterfilelocations.A:

NO–readingmorethanonedatamemorylocationandwritingtomorethanoneregisterfilelocationarenotsupportedduringadatapathoperation.3.Adddatafromtwodatamemorylocationsandstoretheresultinaregisterfilelocation.A:

NO –Doesnotsupportreadingtwodatamemorylocationsduringanoperation –Doesnothaveconnectionsdirectlyfromthedatamemory4.Copydatafromoneregisterfilelocationtoanotherregisterfilelocation.A:

YES–Why?5.Subtractdatainaregisterfilelocationfromadatamemorylocation,storingtheresultinaregisterfilelocation.A:

NO–Valuesreadfromdatamemorymustbeloadedintotheregisterfilefirst.a59BasicDatapathOperationsQ:Whicharevalidsingle-cycleoperations

forgivendatapath?MoveD[1]toRF[1](i.e.,RF[1]=D[1])A:YES–That'saloadoperationStoreRF[1]toD[9]andstoreRF[2]toD[10]A:NO–RequirestwoseparatestoreoperationsAddD[0]plusD[1],storeresultinD[9]A:NO–ALUoperation(ADD)onlyworkswithRF.Requirestwoloadoperations(e.g.,RF[0]=D[0];RF[1]=D[1],anALUoperation(e.g.,RF[2]=RF[0]+RF[1]),andastoreoperation(e.g.,D[9]=RF[2])RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1LoadoperationALUoperationStoreoperationaQ&A6061BasicArchitecture–ControlUnitSupposethebasicdatapathshouldperformthesimpleprocessingtaskofaddingdatamemorylocation0anddatamemorylocation1together,andwritingtheresultindatamemorylocation9.ComputingD[9]=D[0]+D[1]Thisprocessingtaskcanbeachievedby“instructing”thedatapathtoperformthefollowingoperations:Loaddatapathmemorylocation0toregisterRF[0](i.e.,RF[0]=D[0])Loaddatapathmemorylocation1toregisterRF[1](i.e.,RF[1]=D[1])PerformanALUoperationthataddsRF[0]andRF[1]andwritestheresultbackintoRF[2](i.e.,RF[2]=RF[0]+RF[1])StoreRF[2]intodatamemorylocation9(i.e.,D[9]=RF[2]).D[9]=D[0]+D[1]–requiresasequenceoffourdatapathoperations:0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]a62BasicArchitecture–ControlUnitD[9]=D[0]+D[1]–requiresasequenceoffourdatapathoperations:0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]Eachoperationisaninstruction

Sequenceofinstructions–programLookscumbersome,butthat'stheworldofprogrammableprocessors–Decomposingdesiredcomputationsintoprocessor-supportedoperationsStoreprograminInstructionmemoryControlunitreadseachinstructionandexecutesitonthedatapathPC(Programcounter)–addressofcurrentinstructionIR(Instructionregister)–currentinstructionRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]asignalstocontrolthedatapath63BasicArchitecture–ControlUnitTocarryout

eachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapathaRF[0]=D[0]0->1R[0]:??

99"load"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[0]=D[0]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]1(b)ControllerDecodeRegisterfileRFDatamemoryDD[0]:99ALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[0]=D[0]1(c)Executesignalstocontrolthedatapath64BasicArchitecture–ControlUnitaRF[1]=D[1}1->2R[1]:??

102"load"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[1]=D[1]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]2(b)ControllerDecodeRegisterfileRFDatamemoryDD[1]:102ALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[1]=D[1]2(c)ExecutesignalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath65BasicArchitecture–ControlUnitaRF[2]=RF[0]+RF[1]2->3R[2]:??

201"ALU(add)"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[2]=RF[0]+RF[1]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]3(b)ControllerDecodeRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[2]=RF[0]+RF[1]3(c)Execute99102201signalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath66BasicArchitecture–ControlUnitaD[9]=RF[2]3->4R[2]:201"store"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchD[9]=RF[2]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]4(b)ControllerDecodeRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]D[9]=RF[2]4(c)ExecuteD[9]=??201signalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath67BasicArchitecture–ControlUnitRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]signalstocontrolthedatapathControllerFSM68Example:CreatingaSimpleSequenceofInstructionsQ:Createasetofinstructions(orsequence)tocomputeD[3]=D[0]+D[1]+D[2]onearlier-introducedprocessor.A1:OnepossiblesequenceFirstloaddatamemorylocationsintoregisterfileR[3]=D[0]R[4]=D[1]R[2]=D[2](Notearbitraryregisterlocations)Next,performtheadditionsR[1]=R[3]+R[4]R[1]=R[1]+R[2]Finally,storeresultD[3]=R[1]aA2:AlternativesequenceFirstloadD[0]andD[1]andaddthemR[1]=D[0]R[2]=D[1]R[1]=R[1]+R[2]Next,loadD[2]andaddR[2]=D[2]R[1]=R[1]+R[2]aFinally,storeresultD[3]=R[1]Sixinstructionswouldappearininstructionmemorylocations0through569Example:EvaluatingtheNumberofCyclestoExecuteaProgramQ:Howmanycyclesareneededtoexecutesixinstructionsusingtheearlier-describedprocessor?A:Eachinstructionrequires3cycles:1cycletofetchtheinstruction,1cycletodecodethefetchedinstruction,and1toexecutetheinstruction.At3cyclesperinstruction,thetotalcyclesfor6instructionsis6instr*3cycles/instr=18cyclesaThree-InstructionProgrammableProcessorInstructionSet–ListofallowableinstructionsandtheirrepresentationinmemoryReserveacertainnumberofbitsintheinstructiontodenotewhatoperationtoperformRemainingbitsspecifyadditionalinformationneededtoperformtheoperationsuchastheaddressesoftheregistersthatareinvolvedintheoperationThree16bitswideinstructions,leftmost4bitsidentifytheoperation,andtheremaining12bitsidentifytheregisterfileanddatamemoryaddresses:8.3bit11bit10bit9bit8bit7bit6bit5bit4bit3bit2bit1bit0Operationcode0000:Load0001:Store0010:AddAdditionalinformationbit15bit14bit13bit12Three-InstructionProgrammableProcessorThree16bitswideinstructions,e.g.,Loadinstruction —0000r3r2r1r0

d7d6d5d4d3d2d1d0Storeinstruction —0001r3r2r1r0d7d6d5d4d3d2d1d0Addinstruction —0010ra3ra2ra1ra0

rb3rb2rb1rb0rc3rc2rc1rc0718.3InstructionmemoryI0:00000000000000001:00000001000000012:00100010000000013:00010010000010010:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2}DesiredprogramaopcodeoperandsInstructionsin0sand1s–machinecodeaExample:ProgramforThree-InstructionProcessor72RegisterfileRFDatamemoryDALUn-bit2×1DatapathInstructionmemoryIControlunitControllerPCIRsignalstocontrolthedatapath0:00000000000000001:00000001000000012:00100010000000013:00010010000010010:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2}DesiredprogramComputesD[9]=D[0]+D[1]ThedesiredcomputationD[9]=D[0]+D[1]canbewrittenastheprogram:Example:ProgramforThree-InstructionProcessorWriteprogramstoperformthecomputationD[5]=D[5]+D[6]+D[7]usingtheabove-definedthreeinstructionset.73Loadinstruction—0000r3r2r1r0d7d6d5d4d3d2d1d0Storeinstruction—0001r3r2r1r0d7d6d5d4d3d2d1d0Addinstruction—0010ra3ra2ra1ra0rb3rb2rb1rb0rc3rc2rc1rc0Thenumberbeforethecolonrepresentstheinstruction’saddressintheinstructionmemory.Thetextfollowingthetwoforwardslashes“//”representsacomment,andisnotpartofaninstruction.MachineCodevs.AssemblyCodeAprogramrepresentedas0sand1sisknownasmachinecode.Wehumansarenotgoodatwritingandreadingprogramsas0sand1sCan’tunderstandthose0sand1seasilyWillmakeplentyofmistakeswhenwritingsuchprogramsThus,earlycomputerprogrammersdevelopedatoolknownasanassembler(whichitselfisjustanotherprogram)tohelphumanswriteprograms.Allowsustowriteinstructionsusingmnemonics(助記符),orsymbolsAssemblerautomaticallytranslatestomachinecode74AssemblyCodeMachinecode(0sand1s)hardtoworkwithAssemblycode–Usesmnemonics(助記符)Loadinstruction—MOVRa,dspecifiestheoperationRF[a]=D[d].amustbe0,1,...,or15—soR0meansRF[0],R1meansRF[1],etc.dmustbe0,1,...,255?Storeinstruction—MOVd,RaspecifiestheoperationD[d]=RF[a]?Addinstruction—ADDRa,Rb,RcspecifiestheoperationRF[a]=RF[b]+RF[c]750:MOVR0,01:MOVR1,12:ADDR2,R0,R13:MOV9,R20:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]Desiredprogram0:00000000000000001:00000001000000012:00100010000000013:0001001000001001machinecodeassemblycodeTheprogramwrittenusingmnemonicsismucheasiertounderstandthanthe0sand1s,andthatwillbetranslatedtomachinecodebyanassembler(assemblycode).Control-UnitandDatapathforThree-InstructionProcessorTodesignacompletedigitalcircuitforathree-instructionprogrammableprocessor,wecanbeginwithahigh-levelstatemachinedescriptionoftheprocessor'sbehavior76StoreD[d]=RF[ra]op=0001LoadRF[ra]=D[d]op=0000DecodeFetchIR=I[PC]PC=PC+1InitPC=0AddRF[ra]=RF[rb]+RF[rc]op=0010opmeansIR[15..12]rameansIR[11..8]rbmeansIR[7..4]rcmeansIR[3..0]dmeansIR[7..0]executestates簡易處理器設計Control-UnitandDatapathforThree-InstructionProcessorCreatedetailedconnectionsamongcomponents78FetchDecodeInitPC=0StoreIR=I[PC]PC=PC+1LoadAddRF[ra]=RF[rb]+RF[rc]D[d]=RF[ra]RF[ra]=D[d]op=0000op=0001op=0010PCclrup16I_rdPC_incIRId1616R_ldIdatardaddrControllerControlunitDatapathRF_W_wrRF_Rp_addrRF_Rq_addrRF_Rq_rdRF_Rp_rdRF_W_addrD_addr8D_rdD_wrRF_salu_s0addrDrdwr256x1616x16RF16-bit2x1W_dataR_dataRp_dataRq_dataW_dataW_addrW_wrRp_addrRp_rdRq_addrRq_rd0161616161616s1ABs0ALU444PC_clrAssumethat:alu_s0=1,ALUaddsitsinputsalu_s0=0,ALUpassesinputARF_sistheselectlineforthe2x1muxDatamemoryRefineddatapathandcontrolunitforthethree-instructionprocessorInstructionmemoryControl-UnitandDatapathforThree-InstructionProcessorConverthigh-levelstatemachinedescriptionofentireprocessortoFSMdescriptionofcontrollerthatusesdatapathandothercomponentstoachievesamebehavior79FetchDecodeInitPC=0PC_clr=1StoreIR=I[PC]PC=PC+1I_rd=1PC_inc=1IR_ld=1LoadAddRF[ra]=RF[rb]+RF[rc]D[d]=RF[ra]RF[ra]=D[d]op=0000op=0001op=0010D_addr=dD_wr=1RF_s=XRF_Rp_addr=raRF_Rp_rd=1RF_Rp_addr=rbRF_Rp_rd=1RF_s=0RF_Rq_addr=rcRF_Rq_rd=1RF_W_addr=raRF_W_wr=1alu_s0=1D_addr=dD_rd=1RF_s=1RF_W_addr=raRF_W_wr=1aASix-InstructionProgrammableProcessorLet'saddthreemoreinstructions:Load-constantinstruction—0011r3r2r1r0c7c6c5c4c3c2c1c0MOVRa,#c—specifiestheoperationRF[a]=cSubtractinstruction—0100ra3ra2ra1ra0rb3rb2rb1rb0rc3rc2rc1rc0SUBRa,Rb,Rc—specifiestheoperationRF[a]=RF[b]–RF[c]Jump-if-zeroinstruction—0101ra3ra2ra1ra0o7o6o5o4o3o2o1o0JMPZRa,offset—specifiestheoperationPC=PC+offsetifRF[a]is0808.4ExtendingtheControl-UnitandDatapath811:TheloadconstantinstructionrequiresthattheregisterfilebeabletoloaddatafromIR[7..0],inadditiontodatafromdatamemoryortheALUoutput.Thus,wewidentheregisterfile’smultiplexerfrom2x1to3x1,addanothermuxcontrolsignal,andalsocreateanewsignalcomingfromthecontrollerlabeledRF_W_data,whichwillconnectwithIR[7..0].(shownaslabeled1)2:ThesubtractinstructionrequiresthatweuseanALUcapableofsubtraction,soweaddanotherALUcontrolsignal.(shownaslabeled2)3:Thejump-if-zeroinstructionrequiresthatwebeabletodetectifaregisteriszero,andthatwebeabletoaddIR[7..0]tothePC. 3a:Weinsertadatapathcomponenttodetectiftheregisterfile’sRpreadportisallzeros(thatcomponentwouldjustbeaNORgate).(shownaslabeled3a) 3b:WealsoupgradethePCregistersoitcanbeloadedwithPCplusIR[7..0].Theadderusedforthisalsosubtracts1fromthesum,tocompensateforthefactthattheFetchstatealreadyadded1tothePC.(shownaslabeled3b)DatapathRF_Rp_addrRF_Rq_addrRF_Rp_zeroRF_W_addrD_addrD_rdD_wrRF_s1RF_W_dataRF_s0alu_s1alu_s0addrDrdwr256x1616x16RF16-bit3x1W_dataR_dataRp_dataRq_dataW_dataW_addrW_wrRp_addrRp_rdRq_addrRq_rd0161616161616s1s012ABs1s0ALU4443a2=01188s1001s0010ALUoperationpassAthroughA+BA-BPCclrldup16IRId16datardaddrControllerControlunita+b-116**+3bIR[7..0]RF_W_wrRF_Rp_rdRF_Rq_rdExample:ProgramfortheSix-InstructionProcessorExampleprogram–Countnumberofnon-zerowordsinD[4]andD[5]Resultwillbeeither0,1,or2PutresultinD[9]82AssemblycodeCorrespondingmachinecodegeneratedbyanassemblerNote:Thespacesinthemachinecode’s16-bitinstructionsarethereforeaseofreadingbyus,actualmachinecodehasnosuchspaces.FurtherExtensionstotheProgrammableProcessorTypicalprocessorinstructionsetwillcontaindozensofdatamovement(e.g.,loads,stores),ALU(e.g.,add,sub),andflow-of-control(e.g.,jump)instructionsExtendingthecontrol-unit/datapathfollowssimilarlytopreviously-shownextensionsInput/outputextensionsCertainmemorylocationsmayactuallybeexternalpinse.g,D[240]mayrepresent8-bitinputI0,D[255]mayrepresent8-bitoutputP7838.5256x16DW_dataR_dataaddrrdwr0:1:2:239:240:241:248:255:00..000..0I0I1P0P7ProgramusingI/OExtensionsMicroprocessorsacommonchoicetoimplementadigitalsystemEasytoprogramCheap(aslowas$1)Availablenow84I3I4I5I6I7I2I1I0P3P4P5P6P7P2P1P0voidmain(){while(1){P0=I0&&!I1;//F=aand!b,}}0Fba101016:007:057:069:009:01timeDesiredmotion-at-nightdetectorProgrammedmicroprocessorCustomdesigneddigitalcircuitProgramUsingInput/OutputExtensionsUnderlyingassemblycodeforCexpressionI0&&!I1.850:MOVR0,240//moveD[240],whichisthevalueatpinI0,intoR01:MOVR1,241//moveD[241],whichisthatvalueatpinI1,intoR12:NOTR1,R1//compute!I1,assumingexistenceofacomplementinstruction3:ANDR0,R0,R1//computeI0&&!I1,assuminganANDinstruction4:MOV248,R0//moveresulttoD[248],whichispinP0256x16DW_dataR_dataaddrrdwr0:1:2:239:240:241:248:255:00..000..0I0I1P0P7voidmain(){while(1){P0=I0&&!I1;//F=aand!b,}}控制器設計思路控制器主要模塊時序控制模塊取指處理模塊指令譯碼模塊控制指令設計思路--時序控制每條指令的執(zhí)行需要控制單元協(xié)調(diào)多個電路按照規(guī)程進行工作，每個電路所需要的控制信號需要在不同時間內(nèi)生效。幾種參考流程設計自己的控制流程控制指令設計思路--時序控制實現(xiàn)將一次操作采用三個時鐘周期完成。第0個時鐘上升沿鎖存PC，第1個時鐘內(nèi)完成譯指、取數(shù)和運算，第2個時鐘完成存儲器讀或?qū)懸约拜敵黾拇嫫麈i存使能。在第3個時鐘到來時，進行新一輪指令操作。電路主要信號的時序圖時序控制模塊還可以將譯碼的控制結(jié)果在指定時鐘輸出。

CLKmLEmWRmRDmLEmSLEnWRnRDLESLEPCLE功能↑0xxxx-----保持↑10xxx01001PC

PC+1↑110xx10001

↑1xx0x--101

↑1xxx0--011

PCLE：PC鎖存使能LE：通用寄存器Rx鎖存使能SLE：PSR鎖存使能，nRD：輸出存儲器讀取nWR：輸出存儲器載入parameterSI=2'b00,S0=2'b01,S1=2'b10,S2=2'b11;reg[1:0]state=SI;reg[1:0]next_state=S0;

always@(negedgeclk)begin//Thisisacombinationalalwaysblock//if(state==SI)//begin

//endcase(state)SI:next_state=2'b01;S0:next_state=S1;S1:next_state=S2;S2:next_state=S0;//Statetransitionlogicendcaseend

always@(posedgeclk)beginstate=next_state;end

assignnwr=!((state==S2)&&(!mwr));assignnrd=!((state==S2)&&(!mrd));assignle=(state==S2)&&(mle);assignsle=(state==S2)&&(msle);assignpcle=(state==S2);SIS0S1S2再看看指令通過改變處理電路中的信號取值可以實現(xiàn)不同的功能，這些信號取值按序排列構(gòu)成的二進制數(shù)稱為一條操作指令。不同的指令格式指令與字長的關(guān)系控制指令設計思路--取指PC輸出作為指令存儲器的地址輸入，指令存儲器進行片內(nèi)譯碼來選擇相應的指令存儲單元并輸出至指令數(shù)據(jù)總線ID上。指令鎖存信號PCLE鎖存當前總線上的指令代碼并保存在IR中。功能表moduleInst