《信息科學(xué)類專業(yè)英語(yǔ)》課件第8章

Lesson8Top-downSoCDesignMethodology

(第八課自頂向下的SoC設(shè)計(jì)方法學(xué))

Vocabulary(詞匯)ImportantSentences(重點(diǎn)句)QuestionsandAnswers(問答)Problems(問題)

Deepsub-microneffectscomplicatedesignclosureforverylargedesigns.Top-downhierarchicaldesignmethodologycombinedwithphysicalprototypingincreasesdesignproductivityandrestoresschedulepredictability.Inthispaperatop-downhierarchicalflowwillbediscussedanduseofphysicalprototypingtopredicttheperformanceandphysicalcharacteristicsofthefinalphysicalimplementationwillbeexplained.1Top-DownSoCDesignMethodology

System-on-Chip(SoC)designshavebecomeoneofthemaindriversofthesemiconductortechnologyinrecentyears.Multi-milliongatedesignswithmultiplethirdpartyintellectualproperty(IP)coresarecommonplace.SoCdesignersemployIPreusetoimprovedesignproductivity.Previousdesignsdonein-houseorthirdpartydesignscanbeusedasIPinthecurrentdesign.WhileemployingIPcutsdevelopmentcostsandtime,integrationcomplexityincreases.ThisisoneofthemainreasonswhySoCdesignsareimplementedwithhierarchicaltop-downdesignflows(Fig.1).

Theseflowshelptomanagethedifferentandconflictingrequirementsofincreasingdesignsize,deep-submicroneffects(DSM)andthenecessityforshorterandpredictableimplementationtimes.

Hierarchicalmethodologiesallowmultipleteamstoworkondifferentpartsofthedesignconcurrentlyandindependently.This“divideandconquer”approachreducesthecomplexityofthedesignproblemforeachdesignteamandreducesthetimetomarket.FortheSoCdesigns,whicharebuiltfromindependentfunctionblocks,thesecapabilitiesarekeyadvantagesasthefinalimplementationofcomplexchipscanbealengthyprocessandparallelizationcansavevaluabletime.

HierarchicaldesignstylesalsoallowformuchfasterandeasierlateECO’s.Functionalchangesmaybelocalizedtoasingleblockleavingtheremainderofthedesignunaffected.Thislocalizationresultsinfaster,easierECO’s.Anotherreasonforhierarchyistoovercomethecapacitylimitationsofdesigntools.Hierarchicaldesignflowsarescalabletohandledesignscontainingupwardsof100milliongates.

Inadditiontothecomplexitiesthatarearesultoflargedesignsize,deepsub-microneffectsaddtointegrationcomplexitiesandcauselatestagesurprisesandlargeloopsduringthedesigncycle.Fig.1Atop-downhierarchicaldesignmethodology

Indeepsub-microntechnologies,wires,power,routabilityandmanufacturabilityhavetobeconsideredearlyinthedesigncycle.Physicalprototypingprovidesearlyfeedbackintermsofdesignclosureandhelpsvalidatethecorrectnessofdesigndecisions.Physicalprototypingshouldaccuratelypredictthecharacteristicsofthefinalphysicalimplementation.Thiscanbeaccomplishedbyperformingcellplacementandglobalroutingatanappropriatelevelofgranularityneededtoensurethattheprototypecorrelatestothefinalimplementationwithinaspecifiedtolerance.[1]

Traditional,top-downSoCdesignsrelyontheassumptionthatthebudgetingperformedatthechip-levelneednotberevisedaftertheblocksareimplemented.However,unlessveryconservativebudgetsareused,itisimpossibletopredictupfrontwhetherthefinalblockimplementationswillmeetallconstraints.[2]Also,itisdifficulttoadjustthebudgetingifwecannotcapturethephysicalproperties(e.g.,driverstrength,parasitics,currentdrain,etc)thatareobservedattheblockandchipboundaries.

Atop-downhierarchicaldesignmethodologyshouldthereforebecombinedwithphysicalprototypingtoenhancedesignproductivityandrestoreschedulepredictability.Inthispaper,atop-downhierarchicalblock-basedflowwillbediscussedanduseofphysicalprototypingtopredicttheperformanceandphysicalcharacteristicsofthefinalphysicalimplementationwillbeexplained.2HierarchicalSoCDesignFlow

Thecomponentsofapredictabletop-downhierarchicalflowaredesignplanning,physicalprototyping,andimplementation.Atthedesignplanningstage,chiptopography,area,numberofchiplevelpartitionsandtimingbudgetsaredetermined.Duringphysicalprototyping,thedesignplanningresultsarevalidatedforeachblockandforthetop-level.Ifnecessary,correctiveactionistakenbygoingbacktodesignplanningandprogressivelyrefiningthedesign.

Oncephysicalprototypingresultsaresatisfactory,implementationcancommenceconcurrentlyforeachblockandforthetop-level,withtheassurancethatdesign-planningdecisionsarecorrectandimplementationwillbecompletedwithoutanylatesurprises.Top-downplanningandbottom-upprototypingisthemostpredictablewaytoachieveclosureonlargeSoCdesigns.

Designplanningconstitutesanimportantportionofthetop-downhierarchicaldesignflow(Fig.2).TheSoCdesignerevaluatestradeoffswithrespecttotiming,area,andpowerduringdesignplanning.Atthisstage,variousIPcoresfromdifferentvendorsareintegratedintothedesignalongwithcustomlogic.TheIPmaybeprovidedasRTLcode,gatelevelnetlists,orfullyimplementedhardmacros.DecisionsregardingchoicesofdifferentimplementationsofthesameIP,chipandblockaspectratio,budgetingoftop-levelconstraints,standardcellutilization,andotherdesignaspectsaremadeduringdesignplanning.Fig.2Designplanning

Designplanningfunctionsincludepartitioningofthedesign,blockplacementandshaping,hardmacroplacement,pinassignmentandoptimization,toplevelrouteplanning,toplevelrepeaterinsertion,blockbudgetgeneration,andpowerrouting.AllofthesefunctionsarecloselylinkedtotheunderlyingphysicsofDSMtechnology.Forexample,top-levelrepeaterinsertioncannotbedoneproperlywithoutconsideringsignalintegrityandpinscannotbeassignedwithoutconsideringantennarules.

Designplanningcanstartuponavailabilityoftheinitialtop-levelnetlist,evenifthemoduleshavenointernaldefinitionorstructure.Atthisstagemissingmodulesarerepresentedasblackboxes.Theareasofblackboxesareuserdefinedandquicktimingmodelsaregeneratedforsetup/holdarcsandclock-to-outputdelays.Areaestimatesformodulesthathavealreadybeensynthesizedwillbedeterminedbythegatecountanduserdefinedutilization.

Oncethedesignisreadin,andblocksizesaredetermined,aninitialfloorplaniscreatedbyautomaticallyplacingallblocks,shapingthesoftblocks,andpackingtheblockstogetherbasedonglobalroutinginformation.Usingtheblockplacementresults,adjacentblocksmaybeclusteredtogether,orverylargeblocksmaybedividedintosmallerblocks.Modificationsofthephysicalhierarchyatthisstagemaybemadetotakefulladvantageofthephysicalimplementationtools,andtominimizethenumberoftop-levelblocks.

Theblockplacermustalsobeabletoautomaticallyperformsuchoperationsasdeterminethebestaspectratiosforsoftblocksandchoosethebestamongdifferentequivalentimplementationsofhardblocks.AcombinationoftheblockplacerwithamemoryormacrogeneratorleadstooptimizedSoCblocksasthedesignplannerfindsaglobaloptimumbetweenthedifferentpossibleimplementationsandthechipplan.Afterinitialblockplacement,top-downpinassignmentisperformed;top-levelconnectivityandtimingdrivetheplacementofthepinsontheblocks.ForRTLorblackboxmodules,pinassignmentwillhelptocreateblock-levelconstraints.Oncethephysicallocationsofpinsareknown,top-levelnetlengthscanbeestimated.

Foreachblock,aninternaldesignplaniscreated.Macroplacementisdrivenbybothtop-downpinassignmentsthatweredoneinthepreviousstepandinternalmetricssuchasconnectivity,timingandarea.Oncetheinternalplanningforallblockshasbeencompleted,powerrouteplanningisdone.Mostrecenttechnologiesrequireameshstructure.Thepowerroutinggridandblockplacementgridshouldbecarefullysettopreventconnectivityproblemsthatmayariseduetomisalignmentofablockwithrespecttopowergrid.

Afterpowerrouting,pinassignmentsarerefinedusingglobalroutingresults.Theglobalroutercanidentifynarroworwidechannelsandmoveblocksaroundtoopenupcongestedchannelsandconstrictsparseones.Thisenablesoptimumpinplacementforroutabilityduringtheimplementationstage.

AnothercomplexityfacingSoCdesignersduringdesignplanningistop-levelrouteplanning.Netsbetweencriticalblocksmustbeasshortaspossibleandshouldoftenberoutedoverotherblocks.Theseover-the-blocknetsshouldbepusheddownintotheblocksautomatically.Thisrequiresthatanumberofoperationstakeplace.Pinsmustbeassignedtotheblocktoaccommodatethisnewfeedthroughnet.Boththetop-levelandinternalblock-levelnetlistsmustbealteredtoaddconnectivitytothefeedthroughnet.

Top-leveltimingbudgetsmustbeadjustedandinternalblock-levelbudgetsmustbegeneratedtoaccountforglobaltimingclosureandsignalintegrity.Theuseofroutingoverblocksmayevenincludereservingspecialroutingchannelsandemptyplacementareasforrepeaters.Alteringblocksinthiswayconflictswiththegoalofhavingseparated,orevenre-usableSoCblocks,soitdependsontheoverallprojectgoalstowhatextentsuchtechniquesareused.IfTurn-AroundTime(TAT)orre-usearetheprimarygoals,suchtechniquesshouldusedverycarefully.Ifsmallestdiesizeorbestdesignperformanceareprimarygoals,thentheuseoffeedthroughsmaybeessentialtoachievingthegoals.

Duringtimingbudgeting,delayoftop-levelnetsshouldbecalculatedwiththeassumptionthatbufferswillbeaddedtolongorhighfan-outnetsasneeded.Blockbudgetswillbeusedasconstraintstodrivesynthesis,prototyping,andimplementationoftheblocks.

Inpractice,planningmaybeginbeforealloftheblocksarefullyimplemented,soroughestimatesareinitiallyusedinstead.Astheblocksprogressivelygaindefinition,itisnecessarytorelaythenewblockinformationbackuptothechip-level,whereitisincrementallyupdatedandtheappropriateadjustmentsaremade.Thismaytriggerchangesatthechiplevelthatmustbepushedbackdowntotheblocklevel.Thisleadstoatop-downbudgeting,bottom-upprototypingflow,whichismorepredictableandbettersuitedtohandlevariancesbetweenblock-levelconstraintsandactualimplementation.

Althoughitmayappearthatthereisaconflictbetweenearlydesignplanningusingblack-boxmodelsorRTLandnetlist-baseddesignplanningthisisnotthecase;theseactivitiesactuallycomplementeachother(Fig.3).

Earlytop-downdesignplanningisanimportantsteptodriveRTLsynthesisandtogenerateagate-levelnetlistthatisusedtofurtherrefinethedesignplan.Fig.3Designactivitiescomplementeachother

Acharacteristicofthecontinuousplanningandoptimizationprocessistheuseofdifferenttypesofmodelsthatareoptimizedforthedifferentoperationsintheprocess.Thisisillustratedinthefigureabove.

Simpleblockmodelsareusedfordesignplanningandbudgeting.Thephysicalprototypesoftheblocksarebuiltbaseduponthebudgetsfromthedesignplan.Thephysicalprototypesprovidevaluablephysicalinformationaboutthefinalimplementationoftheblocks.Theywillbedescribedinthenextchapter.ThephysicalprototypesarethenusedtoreplacetheblackboxesandRTLmodulesatthetoplevel,sothatwecanrefinethechip-levelconstraints.Whenthefinalbudgetingisresolved,wereturntotheblocksandresumetheirimplementation,andthenwefinishwiththetop-levelchipassembly.

Also,differenttypesofmodelscanbemixedatthetoplevelsinceitislikelythatallprototypeswillnotbecompletedatexactlythesametime.Thisenablesearlyverificationandadjustmentofthechip-levelconstraintsusingacombinationofblackboxesorRTLforsomeblocks,accurateprototypesforothers,andevencompletedphysicallayoutsforsomeoftheblocks.

PhysicalprototypingisanimportantstageofthehierarchicaldesignflowasitprovidesmoredetailsabouttheblockimplementationtotheSoCdesigner.Itbridgesthegapbetweenlogicalandphysicaldesignbyaddingphysicalrealitytotheabstractviewofthedesignplanningprocess.Duringphysicalprototyping,logicoptimizationandglobalplacementareconcurrentlyapplied.Atthisstage,design-planningresultsarevalidatedforeachblockandforthetop-level,andallconflictsareresolved.Theprototypesuncovertheproblems;thecorrectiveactionistakeninthedesignplanningstage.Incompletetimingconstraintscanbediscoveredandaddressedwiththeavailabilityofaccuratephysicalinformation.

PhysicalprototypingisinseparablyconnectedwiththephysicalsynthesisprocessthataddressesmanyDSMissuesbycombiningelementsoflogicsynthesisandphysicalimplementationtogetherintoasinglestage.Physicalsynthesis,asmostpeopleuseittoday,startswithagate-levelnetlistandperformslogicoptimization,placementandglobalrouting,toproduceaplaceddesignthatmeetstimingrequirements.Physicalsynthesismayemploynumeroustechniquestooptimizethelogicalstructureofthechipincluding:gatesizing,buffering,pinswapping,gatecloning,usefulskew,re-synthesisandtechnologyre-mapping,redundancy-basedoptimization,andareaandpowerrecovery.[3]

Thisisasignificantimprovementoverpurelogicsynthesisbecausethelogicoptimizationisperformedandevaluatedbasedoncellplacementthatisindicativeofthefinalplacement.

ItissignificanttonotethatitnolongermakessenseforRTL-to-gatesynthesistoolstoperformsophisticatedgate-leveloptimization.Withoutaccuratephysicalinformation,logicsynthesistoolscannotmakegooddecisionsaboutcellsizingorbuffering.

Physicalsynthesisismuchbettersuitedforthesetasks.Today,theroleofRTL-to-gatelogicsynthesishasbeenreducedtosimplyproducingastructuralgate-levelnetlistasquicklyaspossible,andthenpassitalongtophysicalsynthesiswithoutattemptingtooptimizethesizingorbufferingaspects.ThishasconsequencesforIPcores,whicharedeliveredassoftmacrosfromtheIPvendortotheuserorimplementer.TheIPproviderdeliverseitherthefinalhardmacrooranRTL/netlistandimplementationconstraintstoallowtheoptimizationoftheIPduringtheimplementationoftheSoCchip.

Alltheinformationgeneratedduringthephysicalprototypingofblocksplaysakeyroleinfeedingbackmoreaccurateinformationtothedesignplanningstageforrefinementoftop-leveldesignparameters.

Thephysicalprototypeconsistsofacoarseplacementandoptimizednetlist.Powerrouting,clocktreebuffers,highfan-outnetbufferingmustbeincludedinthephysicalprototype.Withoutanyoftheseitems,physicalprototypewillnotcorrelatetoimplementationandwillnotgiveusefulresults.

Tocreatethephysicalprototype,ahierarchicaltreeofcell-clustersisbuilt

fromtheoriginalnetlistbeforetheplacementstarts.Whilebuildingthetree,functionalhierarchyandconnectivityareconsidered.Then,theblockareaisdividedintoplacementbins,andthecell-clustersareassignedtobinsamonghardmacros.Thecongestionismodeledusingwirescrossingbinboundaries.Duringtheearlystages,thebinsareverycoarseanditisnotusefultomeasuretimingsincemostofthewirecapacitanceisduetointra-binnetsandcanonlybestatisticallyestimated.

Asplacementprogresses,theblockareaisfurtherdividedintosmallerbins,andplacementisrefined,toimprovebothcongestionandwirelength.Thebinscontinuetogetprogressivelysmallerinsizeuntilatsomepoint,theglobalwirescanbeaccuratelyestimated,andintra-binwireuncertaintyisnegligible.Physicalsynthesiscannowstartandthenetlististransformedtomeettimingconstraints.Theplacementisnotyetfinalized,hence,theimpactofnetlistoptimizationoperationssuchaslongnetbuffering,sizing,fan-outoptimization,technologyre-mapping,etc.,canbeeasilyabsorbed.

Similarly,clocktreesynthesiscanbedoneatthephysicalprototypingstageassumingtheleafinstancesareplacedatthecenterofthebins.Congestionandutilizationestimatesaremoreaccuratewiththeinclusionofclocktreebuffers.

Physicalprototypesareusedtovalidatetimingbudgets,areabudgets,IRdrop,congestion,andpinlocations.Thefeedbackfromphysicalprototypingbacktodesignplanningcontainsaccuratetimingabstractions(forrefiningbudgetingattop-level),powermodels(fortop-levelIR-Dropanalysis),andcongestionhotspots,whichneedtobeaddressedbyrelocatingpinsorhardmacroplacement.

Thetop-levelphysicalprototypewillprovidefeedbackontop-leveltimingclosure,routingcongestion,andrequiredchannelareaforbufferingbothclockandsignalnets.

Asthedesignbecomesmoreandmoredefined,theloopsbetweenthedesignplanningstageandprototypingwillconverge.Onceallblocksandthetop-levelaredefined,theSoCdesignerisreadyforimplementation.

Sign-offisthedelineationbetweenthedesignrefinementprocessdescribedaboveandthefinalimplementation.IthaschangedovertimetoaccommodatethenewrequirementsassociatedwithDSMprocesstechnologies.Inthepast,anetlisthand-offwassufficientandprovidedareliableinterfacebetweenlogicalandphysicaldesign.Aswehaveseeninthepreviouschapter,anetlistgeneratedbyRTLsynthesisisnolongerthefinalnetlist.Insteadaprototypecontaininganoptimizednetlistandacoarseorevenfinalplacementareusedtosign-offthedesignpriortofinalimplementation.

Implementationcompletestheprocessbytransformingtheprototypeintoafinalphysicallayout.Implementationoperationsincludedetailedlogicoptimization,placement,androuting.Throughouttheprocess,thedesignisbeingcontinuouslymonitoredfortiming,power,clockskewanddelay,IRdrop,andsignalintegrity.Oncetheblocksarefinished,top-levelassemblyisdone.Sincetheblock-levelimplementationsweredrivenbytop-downconstraints,top-levelsurprisesareeliminated.[4]

Asmentionedabovethestartingpointforfinalimplementationcanbeaprototypewithacourseplacement,inthiscasethefinalimplementationproceedsusingthesametechnologyaswasusedtogeneratethephysicalprototypewithprogressivelysmallerandsmallerbins.Ateachbinlevel,congestion,wirelength,andtimingoptimizationsareincrementallyrun.Ifthestartingpointforimplementationisafinalplacement,thentheimplementationstageproceedswiththeroutingandadjuststheplacementasneeded.

Accurateabstractionsofcompletedblocksareneededtoperformtop-levelassemblyandsign-offthedesignfortapeout.Timingmodelsshouldincludeinterfaceparasitics,accountforsignalintegrity,andshouldbeabletoconsidertimingexceptionsonnetsthatcrossblockboundaries.Physicalmodelsshouldcorrectlyrepresentembeddedwidewires,viacutsneartheboundariesofblocks,antennamodels,andelectromigrationeffects.

Top-levelclocktreesynthesisplaysanimportantroleinreducingholdviolations.Atthetop-level,clocktreesaresynthesizedsuchthatskewtoeachblockinputisadjustedtoaccountfortheinsertiondelayinsidetheblock.Thetop-levelsetupandholdviolationscanbeidentifiedandfixedwithblocktimingabstractsgeneratedusingpropagatedclocks.Theskewtoeachregisterconnectedtoablock-levelclockpinwillbeincludedinthetimingabstractifapropagatedclockisusedduringabstractgeneration.Atthetop-level,setupandholdviolationsbetweenclockscanbeidentifiedandaddressed.3CONCLUSION

IPreuseinSoCsbridgesthedesigngapbyimprovingproductivitybutatthesametime,DSMeffectscomplicateintegration.Theonlywaytorestorepredictabilitytodesigncycleisthroughtop-downdesignplanning,combinedwithfastandaccuratephysicalprototyping.Block-baseddesignplanningaddressesincreasedcomplexity;whilephysicalprototypingrestorespredictabilityandimprovesturnaroundtimebytakingintoaccountuncertaintiesduetowiresandotherDSMeffects.

1.?hierarchicaladj.分層的，分等級(jí)的。

2.?prototypen.原型,雛形,藍(lán)本。

3.?ECO(EngineeringChangeOrder)后期設(shè)計(jì)修正。

4.?upfrontadj.坦率的，誠(chéng)實(shí)的，直爽的；公開的，預(yù)付的,預(yù)交的,先期的adv.在最前面。

5.?parasiticsn.寄生現(xiàn)象，寄生效應(yīng)。

6.?Sign-off簽收。

Vocabulary

[1]Physicalprototypingshouldaccuratelypredictthecharacteristicsofthefinalphysicalimplementation.Thiscanbeaccomplishedbyperformingcellplacementandglobalroutingatanappropriatelevelofgranularityneededtoensurethattheprototypecorrelatestothefinalimplementationwithinaspecifiedtolerance.

物理原型設(shè)計(jì)應(yīng)當(dāng)精確地預(yù)計(jì)最后的物理實(shí)現(xiàn)的特性。這可以通過單元布局和全局布線達(dá)到，而這種布局布線要在適當(dāng)?shù)姆旨?jí)層次上進(jìn)行，以保證相關(guān)的設(shè)計(jì)原型和最終實(shí)現(xiàn)之間的誤差在規(guī)定的容許范圍之內(nèi)。granularity，顆粒度，在這里是電路分級(jí)的粒度。ImportantSentences

[2]Traditional,top-downSoCdesignsrelyontheassumptionthatthebudgetingperformedatthechip-levelneednotberevisedaftertheblocksareimplemented.However,unlessveryconservativebudgetsareused,itisimpossibletopredictupfrontwhetherthefinalblockimplementationswillmeetallconstraints.

傳統(tǒng)的自頂向下SoC設(shè)計(jì)假定芯片級(jí)的預(yù)算在模塊實(shí)現(xiàn)之后不需要修正。但是，除非使用很保守的預(yù)算，否則不可能事先預(yù)計(jì)最終模塊的實(shí)現(xiàn)是否會(huì)滿足所有限制條件。

[3]PhysicalprototypingisinseparablyconnectedwiththephysicalsynthesisprocessthataddressesmanyDSMissuesbycombiningelementsoflogicsynthesisandphysicalimplementationtogetherintoasinglestage.Physicalsynthesis,asmostpeopleuseittoday,startswithagate-levelnetlistandperformslogicoptimization,placementandglobalrouting,toproduceaplaceddesignthatmeetstimingrequirements.Physicalsynthesismayemploynumeroustechniquestooptimizethelogicalstructureofthechipincluding:gatesizing,buffering,pinswapping,gatecloning,usefulskew,re-synthesisandtechnologyre-mapping,redundancy-basedoptimization,andareaandpowerrecovery.把邏輯綜合與物理實(shí)現(xiàn)結(jié)合在一個(gè)階段，物理原型設(shè)計(jì)與處理很多深亞微米問題的物理綜合過程不可分離地聯(lián)系在一起。物理綜合可從門級(jí)網(wǎng)表開始，進(jìn)行邏輯綜合，優(yōu)化、布局和全局布線，產(chǎn)生滿足定時(shí)要求的定位設(shè)計(jì)。物理綜合可以利用很多技術(shù)來優(yōu)化芯片的邏輯結(jié)構(gòu)，包括：門的大小、緩沖、引腳交換、門的復(fù)制、有用的畸變、再綜合和工藝再映射、基于冗余的優(yōu)化，以及面積和電源的恢復(fù)。

[4]Implementationcompletestheprocessbytransformingtheprototypeintoafinalphysicallayout.Implementationoperationsincludedetailedlogicoptimization,placement,