CH7序向邏輯與正反器設(shè)計(jì).ppt

1,序向邏輯與正反器設(shè)計(jì),第七章,儒林圖書(shū)公司 TB061,VHDL數(shù)位電路設(shè)計(jì)實(shí)務(wù)教本 使用Quartus II,Process敘述和If_then_else,2,標(biāo)記名稱:Process （Sensitivity List） begin Process主體敘述 End Process 標(biāo)記名稱;,If (條件1) Then 指令敘述; Elsif (條件2) Then 指令敘述; ： Else 指令敘述; End If;,If_Then_Else 比較指令,Process 敘述,if_then_else敘述 -D型正反器,3,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff_v is PORT( CLK,D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END dff_v; ARCHITECTURE a OF dff_v IS BEGIN PROCESS (CLK) BEGIN IF CLKevent AND CLK=1 THEN Q = D; END IF; END PROCESS; END a;,if_then_else敘述 -AND閘的模擬,4,library IEEE; use IEEE.std_logic_1164.all; entity AND2_vhdl is port ( X : in STD_LOGIC; C : out STD_LOGIC ); end AND2_vhdl; architecture a of AND2_vhdl is begin process (X) begin if X=“11” then C=1; elsif C= 0; end if ; end process; end a;,- define the process section,- the sensitivity list,if_then_else敘述-半加法器設(shè)計(jì),5,library IEEE; use IEEE.std_logic_1164.all; entity halfadd_vhdl is port ( x,y : in STD_LOGIC; sum,carry: out STD_LOGIC ); end halfadd_vhdl; architecture a of halfadd_vhdl is begin process (x, y) begin if (x = 0) and (y = 0) then carry = 0; sum = 0; elsif (x = 0) and (y = 1) then carry = 0; sum = 1;,elsif (x = 1) and (y = 0) then carry = 0; sum = 1; elsif (x = 1) and (y = 1) then carry = 1; sum = 0; end if ; end process; end a;,if_then_else敘述-四對(duì)一多工器,6,方法一：?jiǎn)螌拥腎F-Then-else敘述,Library IEEE; Use ieee.std_logic_1164.all; Entity MUX41 IS PORT(A,B,C,D:IN std_logic; S:IN std_logic_vector(1 downto 0); X:OUT std_logic); END MUX41; Architecture A of MUX41 IS BEGIN PROCESS (s, a, b, c, d) BEGIN,if (s = “00“) then X = a; elsif (s = “01“) then X = b; elsif (s = “10“) then X = c; else X = d; end if; END PROCESS; END a;,if_then_else敘述-四對(duì)一多工器,7,方法二：三層巢狀的IF-Then-else敘述,Library IEEE; Use ieee.std_logic_1164.all; Entity MUX41b IS PORT(A,B,C,D:IN std_logic; S:IN std_logic_vector(1 downto 0); X:OUT std_logic); END MUX41b;,Architecture A of MUX41b IS BEGIN ROCESS (s, a, b, c, d) BEGIN if (s = “00“) then X = a; else if (s = “01“) then X = b; else if (s = “10“) then X = c; else X = d; end if; end if; end if; END PROCESS; END a;,if_then_else敘述-三態(tài)緩衝閘,8,library IEEE; use IEEE.std_logic_1164.all; entity tri_gate is port (oe, X : in std_logic; Y : out std_logic); end tri_gate; architecture a of tri_gate is begin process (oe, X) begin if oe = 1 then Y = X; else Y = Z; end if; end process; end a;,三態(tài)非反相緩衝器在當(dāng)Enable=0時(shí)， 輸出是浮接狀態(tài)（高阻抗輸出）； Enable=1時(shí)，輸出和輸入信號(hào)相同,if_then_else敘述-優(yōu)先權(quán)電路,9,功能設(shè)計(jì)：設(shè)定Y7至Y1是輸入值，Pout是輸出值；其中Y7 是最高優(yōu)先權(quán)的輸入， 而Y1是最低優(yōu)先權(quán)的輸入。 例 如：當(dāng)Y6為1而且Y3也為1時(shí)，其輸出即應(yīng)為1102（610）； 同理當(dāng)Y5為1而且Y2也為1時(shí)，其輸出即應(yīng)為1012（510）,architecture a of priority is begin process (y1, y2,y3, y4, y5, y6, y7) begin if (y7 = 1) then Pout = “111“; elsif (y6 = 1) then Pout = “110“; elsif (y5 = 1) then Pout = “101“; elsif (y4 = 1) then Pout = “100“; elsif (y3 = 1) then Pout = “011“; elsif (y2 = 1) then Pout = “010“; elsif (y1 = 1) then Pout = “001“; else Pout = “000“; end if; end process; end a;,library ieee; use ieee.std_logic_1164.all; entity priority is port ( y1, y2, y3, y4, y5, y6, y7 : in std_logic; Pout: out std_logic_vector(2 downto 0); end priority;,if_then_else敘述-邏輯模組資源分享,10,IF X=1 Then temp1 = A; temp2 = B; else temp1 = C; temp2 = D; End if; Z = temp1 + temp2;,IF X=1 Then Z = A + B; else Z = C + D; End if;,Wait 敘述與標(biāo)準(zhǔn)正反器設(shè)計(jì),11,Wait Until 條件式 Ex：Wait Until CLKevent and CLK=1； Wait On 訊號(hào) Ex： Wait On a,b Wait For 時(shí)間表示式 Ex： Wait For 20ns； Ex： Wait For (a*(b+c);,Wait 敘述,clk,event,以Wait 敘述描述D型正反器,12,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff_v_wait IS PORT( CLK,D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END dff_v_wait; ARCHITECTURE a OF dff_v_wait IS BEGIN PROCESS BEGIN Wait Until (CLKevent AND CLK=1); Q = D; END PROCESS; END a;,簡(jiǎn)易正反器電路應(yīng)用範(fàn)例 -兩個(gè)D型正反器串接的同步電路,13,library ieee; use ieee.std_logic_1164.all; entity D_reg is port (A, CLK : in std_logic; C : out std_logic); end D_reg; architecture a of D_reg is signal B : std_logic; begin PROCESS (clk) BEGIN if CLKevent and CLK=1 then B = A; C = B; end if; END PROCESS; end a;,簡(jiǎn)易正反器電路應(yīng)用範(fàn)例,14,library ieee; use ieee.std_logic_1164.all; entity pulse_form is port(A, CLK: in std_logic; Y : out std_logic); end pulse_form; architecture behavioral of pulse_form is signal B, C, D: std_logic; begin,D_ff: process(CLK) begin if CLKevent and CLK=1 then B = A; C = B; D = C; end if; end process D_ff; Y = C AND (not D); end behavioral;,15,簡(jiǎn)易正反器電路應(yīng)用範(fàn)例-微分電路,library ieee; use ieee.std_logic_1164.all; entity diff_all is port (A, CLK : in std_logic; UP_out,DN_out,UD_out: out std_logic); end diff_all; architecture a of diff_all is signal D0,D1: std_logic;,begin PROCESS (clk) BEGIN if CLKevent and CLK=1 then D0 = A; D1 = D0; end if; END PROCESS; UP_out=D0 and (not D1); -上緣微分 DN_out=(not D0) and D1; -下緣微分 UD_out=D0 xor D1; -上下緣微分 end a;,簡(jiǎn)易正反器電路應(yīng)用範(fàn)例 -四位元的串列輸入移位暫存器設(shè)計(jì),16,LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY d_shift4 IS PORT (D, Clk : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(1 TO 4); END d_shift4; ARCHITECTURE Behavior OF d_shift4 IS SIGNAL Sreg : STD_LOGIC_VECTOR(1 TO 4); BEGIN PROCESS (Clk) BEGIN,IF ClkEVENT AND Clk=1 THEN Sreg(4) = D; Sreg(3) = Sreg(4); Sreg(2) = Sreg(3); Sreg(1) = Sreg(2); END IF; END PROCESS; Q = Sreg; END Behavior;,簡(jiǎn)易正反器電路應(yīng)用範(fàn)例,17,LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sync_ex IS PORT ( clock :in std_logic; Q :out std_logic_vector(2 downto 0); END sync_ex; ARCHITECTURE a OF sync_ex IS signal Qn:std_logic_vector(2 downto 0); BEGIN process(clock) begin if clockevent and clock=1 then Qn(2)=Qn(2) xor (Qn(1) and Qn(0); Qn(1)=Qn(1) xor Qn(0); Qn(0)=not Qn(0); end if; end process; Q=Qn; END a;,具有設(shè)定(Set)與重置(Reset)功能 的正反器設(shè)計(jì) D型正反器,18,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff_v1 is PORT( CLK,D,set,reset : IN STD_LOGIC; Q : OUT STD_LOGIC ); END dff_v1; ARCHITECTURE a OF dff_v1 IS BEGIN PROCESS (CLK) begin if set = 1 then q=1; elsif reset=1 then q=0; elsif CLKevent AND CLK=1 THEN Q = D; end if; END PROCESS; END a;,highest priority,具有設(shè)定(Set)與重置(Reset)功能 的正反器設(shè)計(jì)-JK正反器,19,布林代數(shù)表示式 Q(t+1)=JQ(t)+KQ(t),library ieee; use ieee.std_logic_1164.all; entity JKFF is port (Set, Reset, J, K, CLK: in std_logic; Q : inout std_logic; QN: out std_logic ); end JKFF; architecture a of JKFF is begin process (Set,Reset, CLK) begin if Reset = 1 then Q= 0 ; elsif Set = 1 then Q= 1; elsif CLKevent and CLK = 1 then Q = (J and not Q) or (not K and Q); end if; end process; QN = not Q; end a;,能夠作同步脈波控制功能的 標(biāo)準(zhǔn)正反器設(shè)計(jì),20,為了確保數(shù)組串接的正反器之間CLK訊號(hào)能夠同步動(dòng)作，避免因時(shí)間延遲而導(dǎo)致邏輯單元間的同步問(wèn)題，我們還可以再另外設(shè)計(jì)一個(gè)EN(Enable Clock)準(zhǔn)位來(lái)做同步脈波控制,能夠作同步脈波控制功能的 標(biāo)準(zhǔn)正反器設(shè)計(jì),21,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF IS PORT( CLK,D,set,reset,EN : IN STD_LOGIC; Q : OUT STD_LOGIC ); END DFF; ARCHITECTURE a OF DFF IS BEGIN PROCESS (CLK) BEGIN IF set=1 then Q=1; elsif reset=1 then Q=0; elsif CLKevent AND CLK=1 then IF EN =1 THEN Q = D; END IF; END IF; END PROCESS; END a;,標(biāo)準(zhǔn)正反器應(yīng)用電路範(fàn)例,22,library IEEE; use IEEE.std_logic_1164.all; entity DFF_TP is port (D1, D2, reset, clk: in std_logic; Q : out std_lo