數(shù)字集成電路課件（英文版）：Chapter12 Semiconductor

1、Digital Integrated CircuitsA Design Perspective,Semiconductor Memories,December 20, 2002,Chapter Overview,Memory Classification,Memory Architectures,The Memory Core,Periphery,Reliability Case Studies,Semiconductor Memory Classification,Read-Write Memory,Non-Volatile Read-WriteMemory,Read-Only Memory

2、,EPROM,E,2,PROM,FLASH,Random,Access,Non-Random,Access,SRAM,DRAM,Mask-Programmed,Programmable (PROM,FIFO,Shift Register,CAM,LIFO,Memory Timing: Definitions,Memory Architecture: Decoders,Word 0,Word 1,Word 2,Word,N,2,2,Word,N,2,1,Storage,cell,M,bits,M,bits,N,words,S,0,S,1,S,2,S,N,2,2,A,0,A,1,A,K,2,1,K

3、,5,log,2,N,S,N,2,1,Word 0,Word 1,Word 2,Word,N,2,2,Word,N,2,1,Storage,cell,S,0,Input-Output,M,bits,Intuitive architecture for N x M memory Too many select signals: N words = N select signals,Input-Output,M,bits,Decoder,Array-Structured Memory Architecture,Problem: ASPECT RATIO or HEIGHT WIDTH,Amplif

4、y swing to,rail-to-rail amplitude,Selects appropriate,word,Hierarchical Memory Architecture,Advantages,1. Shorter wires within blocks,2. Block address activates only 1 block = power savings,Block Diagram of 4 Mbit SRAM,Subglobal row decoder,Global row decoder,Subglobal row decoder,Block 30,Block 31,

5、128 K Array Block 0,Block 1,Local row decoder,Hirose90,Contents-Addressable Memory,Address Decoder,I/O Buffers,Commands,2,9,Validity Bits,Priority Encoder,Address Decoder,I/O Buffers,Commands,2,9,Validity Bits,Priority Encoder,Memory Timing: Approaches,Read-Only Memory Cells,WL,BL,WL,BL,1,WL,BL,WL,B

6、L,WL,BL,0,VDD,WL,BL,GND,Diode ROM,MOS ROM 1,MOS ROM 2,MOS OR ROM,WL,0,V,DD,BL,0,WL,1,WL,2,WL,3,V,bias,BL,1,Pull-down loads,BL,2,BL,3,V,DD,MOS NOR ROM,WL,0,GND,BL,0,WL,1,WL,2,WL,3,V,DD,BL,1,Pull-up devices,BL,2,BL,3,GND,MOS NOR ROM Layout,Programmming using the Active Layer Only,Polysilicon,Metal1,Di

7、ffusion,Metal1 on Diffusion,Cell (9.5l x 7l,MOS NOR ROM Layout,Polysilicon,Metal1,Diffusion,Metal1 on Diffusion,Cell (11l x 7l,Programmming using the Contact Layer Only,MOS NAND ROM,All word lines high by default with exception of selected row,WL,0,WL,1,WL,2,WL,3,V,DD,Pull-up devices,BL,3,BL,2,BL,1,

8、BL,0,MOS NAND ROM Layout,Polysilicon,Diffusion,Metal1 on Diffusion,Cell (8l x 7l,Programmming using the Metal-1 Layer Only,NAND ROM Layout,Cell (5l x 6l,Polysilicon,Threshold-alteringimplant,Metal1 on Diffusion,Programmming using Implants Only,Equivalent Transient Model for MOS NOR ROM,Word line par

9、asitics Wire capacitance and gate capacitance Wire resistance (polysilicon) Bit line parasitics Resistance not dominant (metal) Drain and Gate-Drain capacitance,Model for NOR ROM,Equivalent Transient Model for MOS NAND ROM,Word line parasitics Similar to NOR ROM Bit line parasitics Resistance of cas

10、caded transistors dominates Drain/Source and complete gate capacitance,Model for NAND ROM,V,DD,C,L,r,word,c,word,c,bit,r,bit,WL,BL,Decreasing Word Line Delay,Precharged MOS NOR ROM,PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design,WL,0,GND,BL,0,WL,1,WL

11、,2,WL,3,V,DD,BL,1,Precharge devices,BL,2,BL,3,GND,pre,f,Non-Volatile MemoriesThe Floating-gate transistor (FAMOS,Floating gate,Source,Substrate,Gate,Drain,n,n,_,p,t,ox,t,ox,Device cross-section,Schematic symbol,Floating-Gate Transistor Programming,A “Programmable-Threshold” Transistor,FLOTOX EEPROM,

12、Floating gate,Source,Substrate,p,Gate,Drain,n,1,n,1,FLOTOX transistor,Fowler-Nordheim I-V characteristic,20,30 nm,10 nm,10 V,10 V,I,V,GD,EEPROM Cell,WL,BL,Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell,Flash EEPROM,Control gate,erasure,p,substrate,Flo

13、ating gate,Thin tunneling oxide,n,1,source,n,1,drain,programming,Many other options,Cross-sections of NVM cells,EPROM,Flash,Courtesy Intel,Basic Operations in a NOR Flash MemoryErase,Basic Operations in a NOR Flash MemoryWrite,Basic Operations in a NOR Flash MemoryRead,NAND Flash Memory,Unit Cell,Wo

14、rd line(poly,Source line (Diff. Layer,Courtesy Toshiba,NAND Flash Memory,Courtesy Toshiba,Characteristics of State-of-the-art NVM,Read-Write Memories (RAM,STATIC (SRAM,DYNAMIC (DRAM,Data stored as long as supply is applied,Large (6 transistors/cell,Fast,Differential,Periodic refresh required,Small (

15、1-3 transistors/cell,Slower,Single Ended,6-transistor CMOS SRAM Cell,WL,BL,V,DD,M,5,M,6,M,4,M,1,M,2,M,3,BL,Q,CMOS SRAM Analysis (Read,WL,BL,V,DD,M,5,M,6,M,4,M,1,V,DD,V,DD,V,DD,BL,Q,1,Q,0,C,bit,C,bit,CMOS SRAM Analysis (Read,0,0,0.2,0.4,0.6,0.8,1,1.2,0.5,Voltage rise V,1,1.2,1.5,2,Cell Ratio (CR,2.5,

16、3,Voltage Rise (V,CMOS SRAM Analysis (Write,CMOS SRAM Analysis (Write,6T-SRAM Layout,Resistance-load SRAM Cell,M,3,R,L,R,L,V,DD,WL,Q,Q,M,1,M,2,M,4,BL,BL,SRAM Characteristics,3-Transistor DRAM Cell,3T-DRAM Layout,1-Transistor DRAM Cell,Write: C,S,is charged or discharged by asserting WL and BL,Read:

17、Charge redistribution takes places between bit line and storage capacitance,Voltage swing is small; typically around 250 mV,DRAM Cell Observations,1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells

18、. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This

19、 charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD,Sense Amp Operation,1-T DRAM Cell,Uses Polysilicon-Diffusion Capacitance,Expensive in Area,M,1,word,line,Capacitor,Cross-section,Layout,SEM of poly-diffusion capacitor 1T-DRAM,Advanced 1T DRAM Cells,Cell Plat

20、e Si,Capacitor Insulator,Storage Node Poly,2nd Field Oxide,Refilling Poly,Si Substrate,Trench Cell,Stacked-capacitor Cell,Capacitor dielectric layer,Cell plate,Word line,Insulating Layer,Isolation,Transfer gate,Storage electrode,Static CAM Memory Cell,CAM in Cache Memory,Address Decoder,Hit Logic,CA

21、M,ARRAY,Input Drivers,Tag,Hit,Address,SRAM,ARRAY,Sense Amps / Input Drivers,Data,R/W,Periphery,Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry,Row Decoders,Collection of 2M complex logic gates Organized in regular and dense fashion,N)AND Decoder,NOR Decoder,Hierarchical Dec

22、oders,A,2,A,2,A,2,A,3,WL,0,A,2,A,3,A,2,A,3,A,2,A,3,A,3,A,3,A,0,A,0,A,0,A,1,A,0,A,1,A,0,A,1,A,0,A,1,A,1,A,1,WL,1,Multi-stage implementation improves performance,NAND decoder using 2-input pre-decoders,Dynamic Decoders,Precharge devices,V,DD,f,GND,WL,3,WL,2,WL,1,WL,0,A,0,A,0,GND,A,1,A,1,f,WL,3,A,0,A,0

23、,A,1,A,1,WL,2,WL,1,WL,0,2-input NOR decoder,2-input NAND decoder,4-input pass-transistor based column decoder,Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count,2-input NOR decoder,4-to-1 tree based column

24、decoder,Number of devices drastically reduced,Delay increases quadratically with # of sections; prohibitive for large decoders,buffers,progressive sizing,combination of tree and pass transistor approaches,Solutions,BL,0,BL,1,BL,2,BL,3,D,A,0,A,0,A,1,A,1,Decoder for circular shift-register,Sense Ampli

25、fiers,Idea: Use Sense Amplifer,output,input,s.a,small,transition,Differential Sense Amplifier,Directly applicable toSRAMs,M,4,M,1,M,5,M,3,M,2,V,DD,bit,bit,SE,Out,y,Differential Sensing SRAM,Latch-Based Sense Amplifier (DRAM,Initialized in its meta-stable point with EQ,Once adequate voltage gap creat

26、ed, sense amp enabled with SE,Positive feedback quickly forces output to a stable operating point,EQ,V,DD,BL,BL,SE,SE,Charge-Redistribution Amplifier,Concept,M,2,M,3,M,1,V,L,V,S,V,ref,C,small,C,large,Transient Response,Charge-Redistribution AmplifierEPROM,SE,V,DD,WLC,Load,Cascode,device,Column,decod

27、er,EPROM,array,BL,WL,V,casc,Out,C,out,C,col,C,BL,M,1,M,2,M,3,M,4,Single-to-Differential Conversion,How to make a good Vref,Open bitline architecture with dummy cells,C,S,C,S,C,S,C,S,BLL,L,L,1,L,0,R,0,C,S,R,1,C,S,L,BLR,V,DD,SE,SE,EQ,Dummy cell,Dummy cell,DRAM Read Process with Dummy Cell,3,2,1,0,0,1,

28、2,3,V,BL,BL,t,ns,reading 0,3,2,1,0,0,1,2,3,V,SE,EQ,WL,t,ns,control signals,3,2,1,0,0,1,2,3,V,BL,BL,t,ns,reading 1,Voltage Regulator,V,DD,V,REF,V,bias,M,drive,M,drive,V,DL,V,DL,V,REF,Equivalent Model,Charge Pump,DRAM Timing,RDRAM Architecture,memory,array,mux/demux,network,Data,bus,Clocks,Column,Row,

29、demux,packet dec,packet dec,Bus,k,k,3,l,demux,Address Transition Detection,DELAY,t,d,A,0,DELAY,t,d,A,1,DELAY,t,d,A,N,2,1,V,DD,ATD,ATD,Reliability and Yield,Sensing Parameters in DRAM,From Itoh01,4K,10,100,1000,64K,1M,16M,256M,4G,64G,Memory Capacity (bits,chip,C,D,Q,S,C,S,V,DD,V,smax,C,D,1F,C,S,1F,Q,

30、S,1C,V,smax,mv,V,DD,V,Q,S,5,C,S,V,DD,2,V,smax,5,Q,S,C,S,1,C,D,Noise Sources in 1T DRam,C,cross,electrode,a,particles,leakage,C,S,WL,BL,substrate,Adjacent BL,C,WBL,Open Bit-line Architecture Cross Coupling,Sense,Amplifier,C,WL,1,BL,C,BL,C,WBL,C,WBL,C,C,WL,0,C,C,BL,C,C,WL,D,WL,D,WL,0,WL,1,BL,EQ,Folded

31、-Bitline Architecture,Transposed-Bitline Architecture,Alpha-particles (or Neutrons,1 Particle 1 Million Carriers,WL,BL,V,DD,n,1,a,particle,SiO,2,1,1,1,1,1,1,2,2,2,2,2,2,Yield,Yield curves at different stages of process maturity (from Veendrick92,Redundancy,Memory,Array,Column Decoder,Row Decoder,Red

32、undant,rows,Redundant,columns,Row,Address,Column,Address,Fuse,Bank,Error-Correcting Codes,Example: Hamming Codes,with,Redundancy and Error Correction,Sources of Power Dissipation in Memories,PERIPHERY,ROW,DEC,selected,non-selected,CHIP,COLUMN DEC,nC,DE,V,INT,f,mC,DE,V,INT,f,C,PT,V,INT,f,I,DCP,ARRAY,

33、m,n,m(n,2,1)i,hld,mi,act,V,DD,V,SS,I,DD,5,S,C,i,D,V,i,f,1S,I,DCP,From Itoh00,Data Retention in SRAM,A,SRAM leakage increases with technology scaling,Suppressing Leakage in SRAM,SRAM,cell,SRAM,cell,SRAM,cell,V,DD,int,V,DD,V,DD,V,DDL,V,SS,int,sleep,sleep,SRAM,cell,SRAM,cell,SRAM,cell,V,DD,int,sleep,lo

34、w-threshold transistor,Reducing the supply voltage,Inserting Extra Resistance,Data Retention in DRAM,From Itoh00,Case Studies,Programmable Logic Array SRAM Flash Memory,PLA versus ROM,Programmable Logic Array,structured approach to random logic,two level logic implementation,NOR-NOR (product of sums

35、,NAND-NAND (sum of products,IDENTICAL TO ROM,Main difference,ROM: fully populated,PLA: one element per minterm,Note: Importance of PLAs has drastically reduced,1,slow,2,better software techniques (mutli-level logic,synthesis,But,Programmable Logic Array,GND,GND,GND,GND,GND,GND,GND,V,DD,V,DD,X,0,X,0,X,1,f,0,f,1,X,1,X,2,X,2,AND-plane,OR-plane,Pseudo-NMOS PLA,Dynamic PLA,GND,GND,V,DD,V,DD,X,0,X,0,X,1,f,0,f,1,X,1,X,2,X,2,AND,f,AND,f,OR,f,OR,f,AND-plane,OR-plane,Clock Signal Generation for self-timed dynamic PLA,f,t,pre,t,eval,f,AND,f,f,AND,f,AND,f,OR,f,OR,a) Clock signals,