數(shù)字邏輯設(shè)計(jì)及應(yīng)用：第四章 組合邏輯設(shè)計(jì)原理(4)

1、1,Chapter 4 Combinational Logic Design Principles(組合邏輯設(shè)計(jì)原理,Basic Logic Algebra (邏輯代數(shù)基礎(chǔ)) Combinational-Circuit Analysis (組合電路分析) Combinational-Circuit Synthesis (組合電路綜合,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,2,Review of Switching Algebra (開關(guān)代數(shù)內(nèi)容回顧,補(bǔ)充：同或(XNOR)、異或（XOR,Digital Logic Design and

2、Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,3,Review of Switching Algebra (開關(guān)代數(shù)內(nèi)容回顧,補(bǔ)充：同或、異或,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,4,Formula Minimization(公式法化簡(jiǎn),并項(xiàng)法： 利用 AB+AB=A(B+B)=A 吸收法： 利用 A+AB=A(1+B)=A 消項(xiàng)法： 利用 AB+AC+BC = AB+AC 消因子法：利用 A+AB = A+B 配項(xiàng)法： 利用 A+A=A A+A=1,Digital Logic Design and Application (數(shù)字邏輯

3、設(shè)計(jì)及應(yīng)用,5,4.2 Combinational-Circuit Analysis (組合電路分析,Get the Logic Expression or Truth Table from Logic Circuit (由邏輯電路圖得出邏輯表達(dá)式或真值表,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,6,Exhausting Way (窮舉法,圖410） 將全部輸入組合加到輸入端； 根據(jù)基本邏輯關(guān)系，從輸入端到輸出端，寫出每一級(jí)門的輸出； 根據(jù)最后輸出結(jié)果列出真值表,Digital Logic Design and Application (

4、數(shù)字邏輯設(shè)計(jì)及應(yīng)用,7,Algebra Way (代數(shù)法,圖411，12，13，14，15，16，17） 從輸入端到輸出端，逐級(jí)寫出每一級(jí)門的輸出邏輯式； 及時(shí)利用基本定理對(duì)邏輯式化簡(jiǎn)； 由最后輸出端得到輸出函數(shù)式,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,8,Minimize Logic Function (化簡(jiǎn)邏輯函數(shù),什么是最簡(jiǎn),公式法化簡(jiǎn) 卡諾圖化簡(jiǎn),Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,9,Karnaugh Maps(卡諾圖表示邏輯函數(shù),真值表的圖形表示,Digital L

5、ogic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,10,Karnaugh Maps(卡諾圖表示邏輯函數(shù),Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,The coordinates are ordered in Gray codes; Each cell differs from its neighbors in only one variable,11,Karnaugh Maps(卡諾圖表示邏輯函數(shù),真值表的圖形表示,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,1

6、2,Karnaugh Maps(卡諾圖表示邏輯函數(shù),F = (A,B,C)(0,3,5,6,例：填寫下面兩個(gè)函數(shù)的卡諾圖 F1 = (A,B,C) (1,3,5,7) F2(A,B,C) = AC+BCD+B,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,13,卡諾圖的特點(diǎn),邏輯相鄰性： 相鄰兩方格只有一個(gè)因子互為反變量 合并最小項(xiàng) 兩個(gè)最小項(xiàng)相鄰可消去一個(gè)因子 四個(gè)最小項(xiàng)相鄰可消去兩個(gè)因子 八個(gè)最小項(xiàng)相鄰可消去三個(gè)因子 2n個(gè)最小項(xiàng)相鄰可消去n個(gè)因子,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)

7、用,14,兩個(gè)最小項(xiàng)相鄰 可消去一個(gè)因子,XYZ + XYZ = YZ,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,15,四個(gè)最小項(xiàng)相鄰 可消去二個(gè)因子,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,16,A,D,八個(gè)最小項(xiàng)相鄰 可消去三個(gè)因子,F1 = ABC+ABD+ACD+CD+ABC+ACD,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,17,Karnaugh Maps Minimization(卡諾圖化簡(jiǎn),化簡(jiǎn)函數(shù)：F2 = (A,B

8、,C,D) ( 0, 2, 3, 5, 7, 8, 10, 11, 13,ABD,BCD,BC,BD,1、填圖,2、圈組,3、讀圖，得到結(jié)果,F2 = ABD+BCD+BC+BD,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,18,卡諾圖化簡(jiǎn)步驟,填寫卡諾圖 可以先將函數(shù)化為最小項(xiàng)之和的形式 圈組：找出可以合并的最小項(xiàng) 組(圈)數(shù)最少、每組(圈)包含的方塊數(shù)最多 方格可重復(fù)使用，但至少有一個(gè)未被其它組圈過(guò) 讀圖：寫出化簡(jiǎn)后的乘積項(xiàng) 消掉既能為0也能為1的變量 保留始終為0或1的變量,乘積項(xiàng)： 0 反變量 1 原變量,Digital Logic

9、Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,19,圈組原則,圈1，得化簡(jiǎn)“與或式”所有的1必須圈定 圈0，得化簡(jiǎn)“或與式”所有的0必須圈定 每個(gè)圈中0或1的個(gè)數(shù)為 2i 個(gè) a. 首先，保證圈組數(shù)最少 b. 其次，圈組范圍盡量大 c. 每個(gè)圈組至少要有一個(gè)1或0未被其他組圈過(guò),Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,20,圈組步驟,先圈孤立的1格（0格） 再圈只能按一個(gè)方向合并的分組圈子盡量大 其余可任意方向合并 將每個(gè)圈組寫成與項(xiàng)（或項(xiàng)），再進(jìn)行邏輯加（乘,Digital Logic Design and App

10、lication (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,21,卡諾圖法化簡(jiǎn)舉例,F1 = (A,B,C,D) ( 0, 3, 4, 5, 6, 7, 9, 12, 14, 15) F2 = (A,B,C,D) ( 1, 5, 6, 7, 11, 12, 13, 15) F3 = (A,B,C,D) ( 0, 1, 3, 4, 5, 7) F4 = (A,B,C,D) ( 1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,22,Several Concepts (幾 個(gè) 概 念,A logic

11、function P(X1,Xn) implies a logic function F(X1,Xn) if for every input combination such that P=1,then F=1 also. (對(duì)于邏輯函數(shù) P(X1,Xn) 和 F(X1,Xn) ，若對(duì)任何使P=1的輸入組合，也能使F為1，則稱P隱含F(xiàn)，或者F包含P。,P1(A,B,C) = ABC F(A,B,C) = AB + BC P2(A,B,C) = BC,P = A,B,C (1,3,6) F = A,B,C (1,3,5,6,7,Digital Logic Design and Applicati

12、on (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,23,Several Concepts (幾 個(gè) 概 念,A prime implicant of a logic function F(X1,Xn) is a product term P(X1,Xn) that inplies F, such that if any variable is removed from P, then the resulting product term does not imply F. (邏輯函數(shù) F(X1,Xn) 的主蘊(yùn)含項(xiàng) 是隱含 F 的乘積項(xiàng) P(X1,Xn) ，如果從 P 中移去任何變量，則所得的乘積項(xiàng)不隱含F(xiàn)。,F(A

13、,B,C) = ABC + BC + AC = BC + AC,主蘊(yùn)含項(xiàng)定理：最小和是主蘊(yùn)含項(xiàng)之和,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,24,Several Concepts (幾 個(gè) 概 念,蘊(yùn)含項(xiàng)（implicant） ：只包含1的一個(gè)矩形圈； 主蘊(yùn)含項(xiàng)（prime implicant） ：擴(kuò)展到最大的蘊(yùn)含項(xiàng),Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,25,Several Concepts (幾 個(gè) 概 念,Distinguished 1-cell (奇異“ 1 ”單元) An

14、 input combination that is covered by only one prime inplicant (僅被單一主蘊(yùn)含項(xiàng)覆蓋的輸入組合,沒(méi)有可能被重復(fù) “圈”過(guò)的1單元,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,26,Several Concepts (幾 個(gè) 概 念,Essential Prime Implicant (質(zhì)主蘊(yùn)含項(xiàng)) A prime implicant that covers one or more distinguished 1-cell (覆蓋1個(gè)或多個(gè)奇異“1”單元的主蘊(yùn)含項(xiàng),Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,27,Several Concepts (幾 個(gè) 概 念,奇異“ 1 ”單元 僅被單一主蘊(yùn)含項(xiàng)覆蓋的輸入組合,質(zhì)主蘊(yùn)含項(xiàng) 覆蓋1個(gè)或多個(gè)奇異“1”單元的主蘊(yùn)含項(xiàng),圈組時(shí)應(yīng)從合并奇異“1”單元開始,Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用,28,第4章作業(yè)