數(shù)電實(shí)驗(yàn)數(shù)字鐘上機(jī)報(bào)告華科

1、max+plus ii多功能數(shù)字鐘設(shè)計(jì) 自動(dòng)化1001班 劉杰 學(xué)號(hào) u200914402多功能數(shù)字鐘設(shè)計(jì)一、實(shí)驗(yàn)?zāi)康?. 掌握可編程邏輯器件的應(yīng)用開發(fā)技術(shù)設(shè)計(jì)輸入、編譯、仿真和器件編程；2. 熟悉一種eda軟件使用；3. 掌握verilog設(shè)計(jì)方法；二、實(shí)驗(yàn)任務(wù)1. 已知條件max+plus ii軟件fpga實(shí)驗(yàn)開發(fā)裝置(該裝置可以提供3路時(shí)鐘信號(hào)和譯碼顯示電路）基本功能具有“秒”、“分”、“時(shí)”計(jì)時(shí)功能，小時(shí)按24小時(shí)制計(jì)時(shí)。具有校時(shí)功能，能對(duì)“分”和“小時(shí)”進(jìn)行調(diào)整2. 擴(kuò)展功能仿廣播電臺(tái)正點(diǎn)報(bào)時(shí)。在59分51秒、53秒、55秒、57秒、59秒發(fā)出音響結(jié)束時(shí)刻為整點(diǎn)。 定時(shí)控制，其時(shí)間自

2、定；3. 選做內(nèi)容任意時(shí)刻鬧鐘自動(dòng)報(bào)整點(diǎn)時(shí)數(shù)小時(shí)計(jì)數(shù)器改為12翻13、 數(shù)字鐘設(shè)計(jì)分析-功能框圖4、 設(shè)計(jì)編譯 1. 設(shè)計(jì)輸入module top_clock (second,ap,cp,ncr,en,adj_min,adj_hour,ctrlbell,sethrkey,setminkey,alarm,_1khz,_500hz,rhr,rmin); input cp,ncr,en,adj_min,adj_hour,ctrlbell,_1khz,_500hz,sethrkey,setminkey; output7:0 rhr,rmin,second; output alarm; wire7:0

3、set_hr,set_min,hour,minute; wire alarm_clock,alarm_r,alarm_r1; wire _1khz,_500hz,cp; output ap; reg7:0 rhr,rmin,second; supply1 vdd; wire minl_en,minh_en,hour_en,ap; wire hrh_equ,hrl_equ,minh_equ,minl_equ; wire time_equ; /hour:minute:second counter counter10 u1(second3:0,ncr,en,cp); counter6 u2(seco

4、nd7:4,ncr,(second3:0=4h9),cp); assign minl_en=adj_min?vdd:(second=8h59); assign minh_en=(adj_min&(minute3:0=4h9)|(minute3:0=4h9)&(second=8h59); counter10 u3(minute3:0,ncr,minl_en,cp); counter6 u4(minute7:4,ncr,minh_en,cp); assign hour_en=adj_hour?vdd:(minute=8h59)&(second=8h59); counter24 u5(hour7:4

5、,hour3:0,ncr,hour_en,cp,ap);/若鬧鐘調(diào)整使能端開啟，數(shù)碼管顯示鬧鈴設(shè)置時(shí)間，反之顯示時(shí)鐘時(shí)間。 /*always (setminkey or sethrkey) case(setminkey,sethrkey)2b11:begin rmin7:0=set_min7:0;rhr7:0=set_hr7:0; end2b10:begin rmin7:0=set_min7:0;rhr7:0=hour7:0;end2b01:begin rmin7:0=minute7:0;rhr7:0=set_hr7:0;end2b00:begin rmin7:0=minute7:0;rhr7

6、:0=hour7:0;end endcase*/ /選擇類型1always (posedge cp) if(setminkey) rmin7:0=set_min7:0; else rmin7:0=minute7:0; always (posedge cp) if (sethrkey) rhr7:0=set_hr7:0; else rhr7:0=hour7:0;/或者選擇類型2counter10 uc0(set_min3:0,vdd,setminkey,cp); counter6 uc1(set_min7:4,vdd,(set_min3:0=4h9),cp);counter24 su2(set_

7、hr7:4,set_hr3:0,vdd,sethrkey,cp,ap);/comparate the set timecomparator su4(hrh_equ,set_hr7:4,hour7:4);comparator su5(hrl_equ,set_hr3:0,hour3:0);comparator su6(minh_equ,set_min7:4,minute7:4);comparator su7(minl_equ,set_min3:0,minute3:0);assign time_equ=(hrh_equ & hrl_equ & minh_equ & minl_equ);assign

8、alarm_clock=ctrlbell?(time_equ&_500hz):1b0; ring u7(alarm_r,minute,second,_1khz,_500hz);/仿廣播電臺(tái)正點(diǎn)報(bào)時(shí) ring1 u8(alarm_r1,minute,hour,second,_500hz);/自動(dòng)報(bào)整點(diǎn)時(shí)數(shù)assign alarm=alarm_r|alarm_r1|alarm_clock ; /將鬧鐘、報(bào)時(shí)全部歸于揚(yáng)聲器輸出端endmodulemodule counter10(q,ncr,en,cp); input cp,ncr,en; output3:0q; reg 3:0 q; always(

9、posedge cp or negedge ncr) begin if(ncr)q=4b0000; else if(en) q=q; else if(q=4b1001)q= 4b0000; else q=q+1b1; endendmodulemodule counter6(q,ncr,en,cp); input cp,ncr,en; output3:0q; reg 3:0q;always (posedge cp or negedge ncr) begin if(ncr) q=4b0000; else if(en) q=q; else if(q=4b0101) q=4b0000; else q=

10、q+1b1; endendmodule module counter24(cnth,cntl,ncr,en,cp,ap); input cp,ncr,en; output3:0cnth,cntl; output ap;reg 3:0cnth,cntl;reg ap; reg co;always(posedge cp or negedge ncr)begin if(ncr) begin cnth,cntl=8b00010010; ap=1b0;end else if(en)begin cnth,cntl=cnth,cntl;ap1)|(cntl9)|(cnth=1)&(cntl=2) begin

11、 cnth=4b0000; cntl=4b0001;ap=(ap); end else if(cnth=1)&(cntl2) begin cnth=cnth; cntl=cntl+1b1;end else if(cntl=9) begin cnth=cnth+1b1; cntl=4b0000;end else begin cnth=cnth; cntl=cntl+1b1;endendendmodulemodule comparator(equ,a,b);input 3:0a,b;output equ;assign equ=(a=b);endmodule/電臺(tái)報(bào)時(shí)module ring(alar

12、m_r,minute,second,_1khz,_500hz);input _1khz,_500hz;wire _1khz,_500hz;input 7:0minute,second;output alarm_r;reg alarm_r;always (minute or second)if(minute=8h59)case(second)8h51:alarm_r=_500hz;8h53:alarm_r=_500hz;8h55:alarm_r=_500hz;8h57:alarm_r=_500hz;8h59:alarm_r=_1khz;default:alarm_r=1b0;endcaseels

13、e alarm_r=1b0;endmodule/整點(diǎn)報(bào)時(shí)module ring1(alarm_r1,minute,hour,second,_500hz);input _500hz;wire _500hz;input 7:0minute,second,hour;output alarm_r1;reg alarm_r1;always (hour or minute or second)if(minute=8h00)assign alarm_r1=(second=8h01)|(second=8h03)|(second=8h05)|(second=8h07)|(second=8h09)|(second=8h11)|(second=8h13)|(second=8h15)|(second=8h17)|(second=8h19)|(second=8h21)|(second=8h23)&_500hz&(second(hour*2);endmodule 2. 電路仿真圖為起始設(shè)置鬧鐘，由圖可得出鬧鈴設(shè)為1h1min處, 并能觀察出電路仿真自動(dòng)報(bào)整點(diǎn)時(shí)數(shù).在設(shè)置鬧鈴后，可分辨觀察到仿廣播電臺(tái)正點(diǎn)報(bào)時(shí)、自動(dòng)報(bào)整點(diǎn)時(shí)數(shù)5 實(shí)驗(yàn)心得1. 該課程設(shè)計(jì)所設(shè)計(jì)的各種模塊和原理與數(shù)字電子技術(shù)的理論知識(shí)緊密結(jié)合。所以這樣與課本知識(shí)關(guān)聯(lián)緊的課程實(shí)