面向ghz 數(shù)模混合電路的μm inp dhbt工藝

1、0.5m InP DHBT Technology for 100GHz+ Mixed Signal Integrated CircuitsCHENG Wei (程偉)*, ZHANG You-Tao (張有濤), WANG Yuan (王元) , NIU Bin (牛斌), LU Hai-Yan (陸海燕), CHANG Long (常龍), XIE Jun-Ling (謝俊領)Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices I

2、nstitute, Nanjing, 210016, China.*Corresponding author. Email: Abstract: A high performance 3 inch 0.5m InP double heterojunction bipolar transistor (DHBT) technology with three interconnect layers has been developed. The epitaxial layer structure and geometry parameters of the devi

3、ce were carefully studied to get the needed performance. The 0.55m2 InP DHBTs demonstrated ft =350GHz, fmax=532GHz and BVCEO=4.8V, which were modeled using Agilent-HBT large signal model. Static and dynamic frequency dividers designed and fabricated with this technology have demonstrated maximum clo

4、ck frequencies of 114GHz and 170GHz, respectively. The ultra high speed 0.5m InP DHBT technology offers a combination of ultra high speed and high breakdown voltage, which makes it an ideal candidate for next generation 100GHz+ mixed signal integrated circuits.PACS codes:, 85.30.De, 71.55.EqKey word

5、s: InP, heterojunction bipolar transistor, frequency divider面向100GHz+數(shù)?；旌想娐返?.5m InP DHBT工藝程偉，張有濤，王元，牛斌，陸海燕，常龍，謝俊領微波毫米波單片集成和模塊電路重點實驗室，南京電子器件研究所江蘇省南京市中山東路524號，210016摘要: 本文報道了一種高性能的3英寸磷化銦雙異質結雙極型晶體管工藝。Foundation items: Supported by the Natural Science Foundation of Jiangsu Province of China (BK20131072

6、)Biography: CHENG Wei, male, Shandong, China. Ph.D. Research fields focus on InP HBTs and ICs. E-mail: * Corresponding author: E-mail: 發(fā)射極尺寸為0.55m2的磷化銦雙異質結雙極型晶體管，電流增益截止頻率以及最高振蕩頻率分別達到350GHz以及532GHz，擊穿電壓4.8V?；谠摴に囇兄屏?14GHz靜態(tài)分頻器以及170GHz動態(tài)分頻器兩款工藝驗證電路，這兩款電路的工作頻率均處于國內領先水平

7、。關鍵詞: 磷化銦，異質結雙極型晶體管，分頻器中圖分類號: TN322+.8文獻標識碼: AIntroductionThe combination of ultra high speed and high breakdown voltage makes InP double heterojunction bipolar transistors (DHBTs) particularly suitable for high speed mixed signal ICs and sub-MMW MMICs (s-MMICs). To date, several outstanding circuit

8、s have been demonstrated in InP DHBT technology, including static frequency dividers with an operating frequency above 200GHz 1 and 210GHz power amplifiers with an output power above 200mW 2. For mixed signal ICs, the static frequency divider and dynamic frequency divider are usually used as benchma

9、rk circuits for a given device technology. Prior to this work, the highest reported clock rates for the static frequency divider and dynamic frequency divider in an InP DHBT technology were both 100GHz in China 3 4 5. In this paper, we report on the development of a 0.5m InP DHBT technology, optimiz

10、ed for the fabrication of 100GHz+ clock mixed signal ICs. The 0.5m InP DHBTs were modeled using Agilent-HBT (AHBT) large signal models. A static frequency divider and a dynamic frequency divider were fabricated with maximum clock frequencies of 114GHz and 170GHz, respectively.Design and FabricationT

11、he InP DHBT structure was grown using molecular beam epitaxy (MBE) on a 3-inch semi-insulating InP substrate. The InP DHBT epitaxy structure is given in Tab.1, which consists of a thin highly carbon-doped InGaAs base to reduce the base contact resistivity. A base contact resistivity of 3.9-m2 was ex

12、tracted from Transmission Line Model (TLM) measurement on fabricated InP DHBT wafers. A composite collector including an InGaAs setback layer and an InP pulse doping layer was used to eliminate the conduction band spike at the base-collector interface. The more detailed design and optimization metho

13、ds of the composite collector could be found in Ref. 6.Tab.1. InP DHBT epitaxial layer structure表1. InP DHBT外延層結構LayerMaterialThickness (nm)DopantEmitter ContactInGaAs200SiEmitterInP200SiBaseInGaAs35CSet-backInGaAs30Si- dopingInP20SiCollectorInP150SiCollector ContactInGaAs50SiSub-collectorInP200SiEt

14、ch-stopInGaAs10udInP substrateS. I.According to the scaling laws of bipolar transistors, increasing the InP DHBT bandwidth requires both vertical scaling of the epitaxy layer and lateral scaling of the transistor junction dimensions. For this reason, besides the vertical layer structure optimization

15、, the horizontal geometry scaling was also carefully studied in order to reduce the resistive and capacitive parasitics, which were very important to improve the high frequency performances of the HBTs, such as the maximum current gain cutoff frequency (ft) and maximum power gain cutoff frequency (f

16、max). Fig.1 illustrates key geometry parameters of an InP DHBT, including emitter contact width (WEC), emitter contact length (LEC), base contact width (WBC), base contact length (LBC), emitter mesa undercut (WBE) and collector contact width (WCC). Fig.2 shows the expected fmax versus some key geome

17、try parameters. The geometry parameters of the device were carefully designed and optimized under the guidance of these relationships. (a) (b)Fig.1 Key geometry parameters of an InP DHBT: (a) top view; (b) cross section圖1. InP DHBT器件特征尺寸：(a)俯視圖 (b)剖面圖(a) (b)Fig.2. Simulated fmax versus some key geom

18、etry parameters: (a) WEC and WBE; (b) WEC and WBC圖2. fmax隨器件特征尺寸變化曲線:(a) WEC and WBE; (b) WEC and WBCThe InP DHBTs were fabricated using a wet-etch triple mesa process. I-line photolithography was used for all photolithographic process steps. Metal posts on base and collector metals were used to mak

19、e their heights at the same level as that of emitter contact. Thin film NiCr resistor and SiN MIM capacitor fabricated on the InP substrate were used as passive components. BCB was used for device passivation and planarization. The low permittivity dielectric of BCB was also used as the low-loss int

20、erlayer dielectric between the three level metals. In addition, the second metal or the third metal could also be used as the ground plane to form the inverted microstrip environment. The cross section of the 0.5m InP DHBT technology is shown in Fig.3.Fig.3. Cross-section of the 0.5m InP DHBT techno

21、logy圖3. 0.5m InP DHBT工藝剖面圖The Agilent-HBT model was used for large signal modeling the InP DHBTs. This model takes into account various unique properties of InP DHBTs, such as collector transit time modulation with applied bias, base-collector current blocking at high collector currents. Some key pa

22、rameters values of the InP DHBT model are summarized in Tab.2. RE is the emitter resistance of the InP DHBT. RCI and RCX are the intrinsic and extrinsic collector resistances, respectively. RBI and RBX are the intrinsic and extrinsic base resistances, respectively. Cje is the base-emitter capacitanc

23、e and Cjc is the base-collector capacitance. Good agreements between measured and modeled S-parameters were achieved, as shown in Fig.4. The large signal model was then employed in the design of static and dynamic dividers. Tab.2. Key parameters of the InP DHBT model表2. InP DHBT模型關鍵參數(shù)ParameterValueU

24、nitsRE4.27OhmRCI2.03OhmRCX0.49OhmRBI25.24OhmRBX2.40OhmCje15.49fFCjc36.76fFFig.4 Modeled (lines) versus measured (cross symbols) S-parameters圖4. 大信號模型仿真與實測結果對比S參數(shù)A static frequency divider and a dynamic frequency divider were designed as demonstration ICs for the 0.5m InP DHBT technology, which were

25、both highly optimized to obtain peak performances. The dividers were implemented with emitter-coupled-logic (ECL) topology, which could reduce the gate delay compared to the current-model-logic (CML) topology. The emitter followers were inserted between the master and slave latches in order to imple

26、ment impedance transformation and provide appropriate bias for the transistor to obtain the best speed performance. Moreover, in order to maximize the speed and bandwidth of the dividers, peaking inductors were added in series with the load resistances to decrease the transition time. The input and

27、output of the dividers were all designed to be single-ended interfaces for convenient measurement, and the interface circuitry of the divider core was carefully designed to avoid affecting performance of the divider core. The layout of the divider was a very important phase during the whole design.

28、A compact layout could reduce the parasitic capacitance and inductance effectively, which would slow down the divider obviously. A dense wiring scheme and a thin film microstrip line environment were used to reduce the interconnect delays and maintain the signal integrity. Moreover, some key transmi

29、ssion lines were simulated in the ADS momentum to take into account both the transmission line effect and signal integrity. Fig.5 illustrates the simplified schematics of the static and dynamic frequency dividers. The maximum simulated toggle rates for the static and dynamic dividers were 140GHz and

30、 212GHz, respectively.(a) (b)Fig.5 Simplified schematic of the divider core: (a) static divider; (b) dynamic divider圖5. 分頻器核心原理圖:(a)靜態(tài)分頻器 (b)動態(tài)分頻器Measurement and DiscussionAfter fabrication, measurements for the InP DHBTs were performed at room temperature. The microscope picture of the InP DHBT is

31、shown in Fig.6, the area of the single emitter finger is 0.55m2 and the base contact width is 0.5m at each side of the emitter. The DC characteristics of the fabricated InP DHBTs were measured using B1500 semiconductor parameter analyzer. Common-emitter current-voltage characteristics of an InP DHBT

32、 with an emitter area of 0.55m2 are shown in Fig.7. The current gain () is 33 and the common-emitter breakdown voltage (BVCEO) is 4.8V. The offset and the knee voltages are 0.1V and 0.5V, respectively. The small knee voltage and sharp current rising indicate that the current blocking effect has been

33、 successfully suppressed by the composite collector 7.Fig.6. Microscope picture of a 0.55m2 DHBT圖6. 0.55m2 DHBT器件顯微鏡照片F(xiàn)ig.7. Common-emitter current-voltage characteristics of a 0.55m2 DHBT圖7 發(fā)射極面積0.55m2 DHBT器件I-V特性曲線On-wafer small-signal RF performance was measured with N5247A vector network analyze

34、r from 0.2 to 67GHz after performing a standard short-open-load-through (SOLT) calibration. On-wafer short and open pad structures identical to those used by the InP DHBTs were measured to deembed the pad parasitics. Fig.8 shows the measured current gain (H21), maximum stable/available gain (MSG/MAG

35、) and Masons unilateral Gain (U) as functions of frequency of a 0.55m2 InP DHBT. The small jitter of the measured U was caused by the resonant hole modulation 8. ft and fmax were extracted from the measured H21 and U by using a -20dB/decade slope, respectively, at a bias condition of VCE=1.5V and IC

36、=11mA. The extrapolated ft and fmax of a 0.55m2 InP DHBT are 350GHz and 532GHz, respectively. Fig.9 shows variation of ft and fmax versus collector current density (Jc) at VCE=1.5V and the Kirk effect is observed at a Jc of 4.8mA/m2 when ft falls to 95% of its peak value. Table 3 compares recently r

37、eported InP DHBTs in China.Fig.8. H21, MSG/MAG and U for a 0.55m2 DHBT versus frequency at VCE=1.5V and IC=11mA圖8. 發(fā)射極面積0.55m2 DHBT器件H21, MSG/MAG以及U隨頻率變化曲線Fig.9. Extrapolated ft and fmax of a 0.55m2 DHBT versus Jc at VCE=1.5V圖9. 發(fā)射極面積0.55m2 DHBT器件ft 以及fmax隨電流密度變化曲線Tab.3. Comparison of InP DHBTs 表3.

38、InP DHBT性能比較Ref.Technologyft (GHz) fmax (GHz)71.6m InP DHBT24210690.5m InP DHBT- 416101.0m InP DHBT170256This wok0.5m InP DHBT350532After fabrication, the static and dynamic frequency dividers were measured at room temperature on a wafer probe station. A conventional 50GHz CW source was used for low

39、 frequency measurement. Testing beyond 50GHz in the V, W and D-bands was performed with combination of low frequency source and frequency multiplier modules. The output spectrum of the divider was measured by a 50GHz spectrum analyzer. V-band or W-band harmonic mixer modules were used on the divider

40、 output when testing above 100GHz or 150GHz.The maximum clock rates achievable for the static frequency and dynamic frequency dividers were 114GHz and 170GHz, respectively. The maximum simulated toggle rates of the dividers were a little higher than those measured from the fabricated circuits, which

41、 was probably because only some key but not all of the transmission lines were taken into account during the circuit design process to reduce the time and complexity of the EM simulation. Moreover, the large signal model of the InP DHBT was implemented based on the measurement data from 200MHz to 67

42、GHz, so there were some errors in the simulation results especially in the frequency range beyond 67GHz. Fig.10 and Fig.11 illustrate the measured output spectrums for the static and dynamic frequency dividers, respectively. Table 4 compares the performances of recently reported static and dynamic f

43、requency dividers in China. (a) (b)Fig.10. Output spectrums for the static frequency divider: (a) 2GHz input; (b) 114GHz input圖10. 靜態(tài)分頻器輸出頻譜: (a)輸入頻率2GHz (b)輸入頻率114GHz (a) (b)Fig.11. Output spectrums for the dynamic frequency divider: (a) 110GHz input; (b) 170GHz input圖11. 動態(tài)分頻器輸出頻譜: (a)輸入頻率110GHz (

44、b)輸入頻率170GHzTab.4. Comparison of InP DHBT static and dynamic frequency dividers表4. InP DHBT靜態(tài)和動態(tài)分頻器性能比較Ref.TypeTechnologyft / fmax(GHz)Max. operating freq. (GHz)DC power(mW)3Static0.7m InP DHBT280 / 280833504Dynamic1.0m InP DHBT214 / 1938310605Static1.4m InP DHBT170 / 25340650This wokStatic0.5m InP

45、DHBT350 / 532114600This workDynamic0.5m InP DHBT350 / 532170550Although ft and fmax could be used to describe the maximum operating frequency the InP DHBT, they are of limited value in predicting the speed of the high speed mixed-signal ICs. In fact, static and dynamic frequency dividers are usually

46、 used as benchmark circuits for a given device technology. The propagation delay of the divider is dependent on the charging times of the parasitic capacitances and resistances encountered in the signal path, which could be calculated using the method of open circuit time constants (MOTC). The most

47、significant delay part is CcbVlogic/Ic, where Ccb is the capacitance of the base-collector junction, Vlogic is the logic swing of the circuit, and Ic is the collector current. Therefore, a smaller Ccb and a higher current density are preferred to increase the digital circuit speed. For the current d

48、ensity, as the current density increases, the mobile carriers modify the electric field profile. When the electron concentration in the base-collector depletion region exceeds the doping density of the collector, the electric field of the collector at the base side will reach zero, the Kirk effect t

49、hus occurs and the corresponding collector current density is Kirk current density (JKirk). The Kirk effect causes an additional electron barrier at the base-collector interface, which degrades the DC and RF performances of the InP DHBT, so the operating current density of the InP DHBT in the circui

50、t should be close to but less than JKirk.The Kirk current density could be derived as follows:JKirk=2seff(Vbi+Vcb-EC(Ts+Tg)/qTg)/TC2+qNCeff (1) s is the dielectric constant of the semiconductor.NC and TC are the doping concentration and thickness of the collector. eff is the effective velocity of th

51、e electrons in the collector, Ts is the thickness of the setback layer, Vbi is the built-in voltage of the base-collector junction and Vcb is the applied voltage. According to Eq. (1), the Kirk current is inversely proportional to the square of collector thickness, so a thinner collector is helpful

52、to improve the current density. The thickness of the collector has been reduced from 250 nm in Ref. 3 to 200nm in this study, which means that the current density will increase about 1.56 times according to Eq. (1) and this is helpful to improve the speed of the mixed-signal circuit.Base-collector c

53、apacitance (Ccb) is another critical factor limiting the speed of the mixed-signal circuit. Ccb could be derived as follows:Ccb=sAcb/TC=s(2WBC + WEC) LBC /TC (2)Acb is the base collector area. According to Eq. (2), Ccb is proportional to the base collector area, so a smaller base collector junction

54、is helpful to reduce the base collector capacitance. The width of the emitter contact has been reduced from 0.7 m in Ref. 3 to 0.5 m in this study and the width of the base contact from 1.0 m to 0.5 m. By using smaller emitter and base contacts, the base collector area has been reduced about 45% res

55、ulting into lower base-collector capacitance. ConclusionIn summary, a 0.5m InP DHBT technology has been developed. A 0.55m2 emitter area device demonstrated ft =350GHz, fmax=532GHz and BVCEO=4.8V. A 114GHz static frequency divider and a 170GHz dynamic frequency divider were designed, fabricated and demonstrated with this technology. The 0.5m InP DHBT technology offers a combination of ultra high speed and high breakdown voltage, which makes it suitable for high performance digital and mixed signal applications.Re