八路智能搶答器的設(shè)計單片機畢業(yè)設(shè)計外文翻譯單片機AT89C

1、at89c51features compatible with mcs-51 products 4k bytes of in-system reprogrammable flash memory endurance: 1,000 write/erase cycles fully static operation: 0 hz to 24 mhz three-level program memory lock 128 x 8-bit internal ram 32 programmable i/o lines two 16-bit timer/counters six interrupt sour

2、ces programmable serial channel low-power idle and power-down modesdescriptionthe at89c51 is a low-power, high-performance cmos 8-bit microcomputer with 4kbytes of flash programmable and erasable read only memory (perom). the deviceis manufactured using atmels high-density nonvolatile memory technol

3、ogy and iscompatible with the industry-standard mcs-51 instruction set and pinout. the on-chipflash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. by combining a versatile 8-bit cpu with flashon a monolithic chip, the atmel at89c51 is a powe

4、rful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control applications.the at89c51 provides the following standard features: 4kbytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full

5、 duplex serial port, on-chip oscillator and clock circuitry.in addition, the at89c51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. the idle modestops the cpu while allowing the ram, timer/counters,serial port and interrupt s

6、ystem to continue functioning. thepower-down mode saves the ram contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.pin configurations pin descriptionvcc：supply voltage.gnd：ground.port 0：port 0 is an 8-bit open-drain bi-directional i/o port. as anoutput

7、 port, each pin can sink eight ttl inputs. when 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data memory. in this mode p0 has internalpullups.port 0 also r

8、eceives the code bytes during flash programming,and outputs the code bytes during programverification. external pullups are required during program verification.port 1：port 1 is an 8-bit bi-directional i/o port with internal pullups.the port 1 output buffers can sink/source four ttl inputs.when 1s a

9、re written to port 1 pins they are pulled high bythe internal pullups and can be used as inputs. as inputs,port 1 pins that are externally being pulled low will source current (iil) because of the internal pullups.port 1 also receives the low-order address bytes during flash programming and verifica

10、tion.port 2：port 2 is an 8-bit bi-directional i/o port with internal pullups.the port 2 output buffers can sink/source four ttl inputs.when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally being pulled lo

11、w will source current (iil) because of the internal pullups.port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx dptr). in this application, it uses strong internal pullups when emitting 1s. d

12、uring accesses to external data memory that use 8-bit addresses (movx ri), port 2 emits the contents of the p2 special function register.port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3：port 3 is an 8-bit bi-directional i/o po

13、rt with internal pullups.the port 3 output buffers can sink/source four ttl inputs.when 1s are written to port 3 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 3 pins that are externally being pulled low will source current (iil) because of the pullups.po

14、rt 3 also serves the functions of various special features of the at89c51 as listed below:port 3 also receives some control signals for flash programmingand verification.ale/prog：address latch enable output pulse for latching the low byte of the address during accesses to external memory. this pin i

15、s also the program pulse input (prog) during flash programming.in normal operation ale is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory.if de

16、sired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode.psen：program sto

17、re enable is the read strobe to external program memory.when the at89c51 is executing code from external programmemory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory.ea/vpp：external access enable. ea must be strapp

18、ed to gnd in order to enable the device to fetch code from external program memory locations starting at 0000h up to ffffh.note, however, that if lock bit 1 is programmed, ea will be internally latched on reset. ea should be strapped to vcc for internal program executions. this pin also receives the

19、 12-volt programming enable voltage (vpp) during flash programming, for parts that require 12-volt vpp.xtal1：input to the inverting oscillator amplifier and input to the internal clock operating circuit.xtal2：output from the inverting oscillator amplifier.oscillator characteristicsxtal1 and xtal2 ar

20、e the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 1. either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is

21、driven as shown in figure 2. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.idle modein idle mode, the

22、 cpu puts itself to sleep while all the onchip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. it sho

23、uld be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pin

24、s is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory.figure 1. oscillator connectionsfigure 2. external clock drive

25、 configurationpower-down modein the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. the on-chip ram and special function registers retain their values until the power-down mode is terminated. the only exit from power-down is a

26、 hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.program memory lock bitson the chip are three loc

27、k bits which can be left unprogrammed (u) or can be programmed (p) to obtain the additional features listed in the table below.when lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a ran

28、dom value, and holds that value until reset is activated. it is necessary that the latched value of ea be in agreement with the current logic level at that pin in order for the device to function properly.programming the flashthe at89c51 is normally shipped with the on-chip flash memory array in the

29、 erased state (that is, contents = ffh) and ready to be programmed. the programming interface accepts either a high-voltage (12-volt) or a low-voltage (vcc) program enable signal. the low-voltage programming mode provides a convenient way to program the at89c51 inside the users system, while the hig

30、h-voltage programming mode is compatible with conventional thirdparty flash or eprom programmers. the at89c51 is shipped with either the high-voltage or low-voltage programming mode enabled.the at89c51 code memory array is programmed byte-bybyte in either programming mode. to program any nonblank by

31、te in the on-chip flash memory, the entire memory must be erased using the chip erase mode.at89c51主要性能參數(shù)：l 與mcs-51產(chǎn)品指令系統(tǒng)完全兼容l 4k字節(jié)可重檫寫flash閃速存儲器l 1000次檫寫周期l 全靜態(tài)操作：0hz-24mhzl 三級加密程序存儲器l 128*8字節(jié)內(nèi)部raml 32個可編程i/o口線l 2個16位定時/記數(shù)器l 6個中斷源l 可編程串行uart通道l 低功耗空閑和掉電模式功能特性概述：at89c51提供以下標(biāo)準(zhǔn)功能：4k字節(jié)flash閃速存儲器，128字節(jié)內(nèi)部

32、ram，32個i/o口線，兩個16位定時/記數(shù)器，一個5向量兩級中斷結(jié)構(gòu)，一個全雙工串行通信口，片內(nèi)振蕩器及時鐘電路。同時，at89c51可降至0hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止cpu的工作，但允許ram，定時/記數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存ram中的內(nèi)容，但振蕩器停止工作直到下一個硬件復(fù)位。at89c51是美國atmel公司生產(chǎn)的低電壓，高性能cmos的8位單片機，片內(nèi)含4k bytes的可反復(fù)擦寫的只讀程序存儲器（perom）和128 bytes的隨機存取數(shù)據(jù)存儲器（ram），器件采用atmel公司的高密度、非易失性存儲技術(shù)生產(chǎn)，兼容標(biāo)

33、準(zhǔn)mcs-51指令系統(tǒng)，片內(nèi)置通用8位中央處理器（cpu）和flash存儲單元，功能強大at89c51單片機可為您提供許多高性價比的應(yīng)用場合，可靈活應(yīng)用于各種控制領(lǐng)域。引腳功能說明vcc：電源電壓gnd：地p0 口：p0 口是一組8 位漏極開路型雙向io 口，也即地址數(shù)據(jù)總線復(fù)用口。作為輸出口用時，每位能吸收電流的方式驅(qū)動8個ttl邏輯門電路，對端口寫“1”可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲器或程序存儲器時，這組口線分時轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。在fiash編程時，p0口接收指令字節(jié)，而在程序校驗時，輸出指令字節(jié)，校驗時，要求外接上拉電阻。p1口：p1

34、是一個帶內(nèi)部上拉電阻的8位雙向io口，p1的輸出緩沖級可驅(qū)動（吸收或輸出電流）4個ttl邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口。作輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（iil）。fiash編程和程序校驗期間，p1接收低8位地址。p2口：p2是一個帶有內(nèi)部上拉電阻的8位雙向io口，p2的輸出緩沖級可驅(qū)動（吸收或輸出電流）4個ttl邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口，作輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（iil）。在訪問外部程序存儲器或1

35、6位地址的外部數(shù)據(jù)存儲器（例如執(zhí)行movxdptr指令）時，p2口送出高8位地址數(shù)據(jù)。在訪問8 位地址的外部數(shù)據(jù)存儲器（如執(zhí)行movxri 指令）時，p2 口線上的內(nèi)容（也即特殊功能寄存器（sfr）區(qū)中r2寄存器的內(nèi)容），在整個訪問期間不改變。flash編程或校驗時，p2亦接收高位地址和其它控制信號p3口：p3口是一組帶有內(nèi)部上拉電阻的8 位雙向io 口。p3 口輸出緩沖級可驅(qū)動（吸收或輸出電流）4 個ttl邏輯門電路。對p3 口寫入“1”時，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時，被外部拉低的p3 口將用上拉電阻輸出電流（iil）。p3口除了作為一般的io口線外，更重要的用途是它

36、的第二功能，如下表所示：p3.0rxd（串行輸入口）p3.1txd（串行輸出口）p3.2int0（外中斷0）p3.3int1（外中斷1）p3.4t0（定時/計數(shù)器0外部輸入）p3.5t1（定時/計數(shù)器1外部輸入）p3.6wr（外部數(shù)據(jù)存儲器寫選通）p3.7rd（外部數(shù)據(jù)存儲器讀選通）p3口還接收一些用于flash閃速存儲器編程和程序校驗的控制信號。rst：復(fù)位輸入。當(dāng)振蕩器工作時，rst引腳出現(xiàn)兩個機器周期以上高電平將使單片機復(fù)位。aleprog： 當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時，ale（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲器，ale 仍以時鐘振蕩頻率的l6

37、輸出固定的正脈沖信號，因此它可對外輸出時鐘或用于定時目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時將跳過一個ale脈沖。對flash存儲器編程期間，該引腳還用于輸入編程脈沖（prog）。如有必要，可通過對特殊功能寄存器（sfr）區(qū)中的8eh單元的do 位置位，可禁止ale 操作。該位置位后，只有一條movx和movc指令ale才會被激活。此外，該引腳會被微弱拉高，單片機執(zhí)行外部程序時，應(yīng)設(shè)置ale無效。psen：程序儲存允許（psen）輸出是外部程序存儲器的讀選通信號，當(dāng)at89c51 由外部程序存儲器取指令（或數(shù)據(jù)）時，每個機器周期兩次psen有效，即輸出兩個脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲器

38、，這兩次有效的psen信號出現(xiàn)。eavpp：外部訪問允許。欲使cpu僅訪問外部程序存儲器（地址為0000hffffh），ea端必須保持低電平（接地）。需注意的是：如果加密位lb1被編程，復(fù)位時內(nèi)部會鎖存ea端狀態(tài)。如ea端為高電平（接vcc端），cpu則執(zhí)行內(nèi)部程序存儲器中的指令。flash存儲器編程時，該引腳加上+12v的編程允許電源vpp，當(dāng)然這必須是該器件是使用12v編程電壓vpp。xtal1：振蕩器反相放大器的及內(nèi)部時鐘發(fā)生器的輸入端。xtal2：振蕩器反相放大器的輸出端。時鐘振蕩器：at89c5l 中有一個用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳xtal1 和xtal2 分別是該放

39、大器的輸入端和輸出端。這個放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5。外接石英晶體（或陶瓷諧振器）及電容c1、c2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對外接電容c1、c2雖然沒有十分嚴(yán)格的要求，但電容容量的大小會輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30pf10pf，而如使用陶瓷諧振器建議選擇40pf10f。用戶也可以采用外部時鐘。采用外部時鐘的電路如圖5右圖所示。這種情況下，外部時鐘脈沖接到xtal1端，即內(nèi)部時鐘發(fā)生器的輸入端，xtal2則懸空。圖1內(nèi)部振蕩電路圖 2外部時鐘驅(qū)動

40、電路石英晶體時：c1，c230pf10pf 陶瓷濾波器：c1，c240pf10pf由于外部時鐘信號是通過一個2分頻觸發(fā)器后作為內(nèi)部時鐘信號的，所以對外部時鐘信號的占空比沒有特殊要求，但最小高電平持續(xù)時間和最大的低電平持續(xù)時間應(yīng)符合產(chǎn)品技術(shù)條件的要求?？臻e節(jié)電模式：at89c51 有兩種可用軟件編程的省電模式，它們是空閑模式和掉電工作模式。這兩種方式是控制專用寄存器pcon（即電源控制寄存器）中的pd（pcon.1）和idl（pcon.0）位來實現(xiàn)的。pd 是掉電模式，當(dāng)pd=1 時，激活掉電工作模式，單片機進(jìn)入掉電工作狀態(tài)。idl是空閑等待方式，當(dāng)idl=1，激活空閑工作模式，單片機進(jìn)入睡眠狀

41、態(tài)。如需同時進(jìn)入兩種工作模式，即pd和idl同時為1，則先激活掉電模式。在空閑工作模式狀態(tài)，cpu保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時，片內(nèi)ram和所有特殊功能寄存器的內(nèi)容保持不變。空閑模式可由任何允許的中斷請求或硬件復(fù)位終止。終止空閑工作模式的方法有兩種，其一是任何一條被允許中斷的事件被激活，idl（pcon.0）被硬件清除，即刻終止空閑工作模式。程序會首先響應(yīng)中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行完中斷服務(wù)程序并緊隨reti（中斷返回）指令后，下一條要執(zhí)行的指令就是使單片機進(jìn)入空閑模式那條指令后面的一條指令。其二是通過硬件復(fù)位也可將空閑工作模式終止。需要注意的是，當(dāng)由

42、硬件復(fù)位來終止空閑工作模式時，cpu 通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個機器周期（24個時鐘周期）有效，在這種情況下，內(nèi)部禁止cpu訪問片內(nèi)ram，而允許訪問其它端口。為了避免可能對端口產(chǎn)生意外寫入，激活空閑模式的那條指令后一條指令不應(yīng)是一條對端口或外部存儲器的寫入指令。掉電模式：在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)ram 和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變ram中的內(nèi)容，在vcc恢復(fù)到正常工作電平前

43、，復(fù)位應(yīng)無效，且必須保持一定時間以使振蕩器重啟動并穩(wěn)定工作。程序存儲器的加密：at89c51 可使用對芯片上的3 個加密位lb1、lb2、lb3 進(jìn)行編程（p）或不編程（u）來得到如下表所示的功能加密位保護(hù)功能表：當(dāng)加密位lb1 被編程時，在復(fù)位期間，ea端的邏輯電平被采樣并鎖存，如果單片機上電后一直沒有復(fù)位，則鎖存起的初始值是一個隨機數(shù)，且這個隨機數(shù)會一直保存到真正復(fù)位為止。為使單片機能正常工作，被鎖存的ea 電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除。flash閃速存儲器的編程：at89c51 單片機內(nèi)部有4k 字節(jié)的flash perom，這個flash

44、 存儲陣列出廠時已處于擦除狀態(tài)（即所有存儲單元的內(nèi)容均為ffh），用戶隨時可對其進(jìn)行編程。編程接口可接收高電壓（+12v）或低電壓（vcc）的允許編程信號。低電壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用eprom編程器兼容。at89c51單片機中，有些屬于低電壓編程方式，而有些則是高電壓編程方式，用戶可從芯片上的型號和讀取芯片內(nèi)的名字節(jié)獲得該信息。at89c51的程序存儲器陣列是采用字節(jié)寫入方式編程的，每次寫入一個字節(jié)，要對整個芯片內(nèi)的perom程序存儲器寫入一個非空字節(jié)，必須使用片擦除的方式將整個存儲器的內(nèi)容清除。核準(zhǔn)通過，歸檔資料。未經(jīng)允許，請勿外傳！9jwkffwvg#t

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