AltiumDesigner高級覆銅布線規(guī)則

1、Altium desig ner PCB adva nee rulesSEED20覆銅咼級連接萬式如過孔全連接，焊盤熱焊盤連接；頂層GND網(wǎng)絡(luò)全連接，其他層熱焊盤連接線寬0.3mm|在 AD PCB 環(huán)境下，DesignRulesPlane Polygon Conneet style，點(diǎn)中 Polygon Conneet style，右鍵點(diǎn)擊 new rule 新建一個規(guī)則點(diǎn)擊新建的規(guī)則既選中該規(guī)則，在name框中改變里面的內(nèi)容即可修改該規(guī)則的名稱，默認(rèn)是Polyg on Co nn eet_1 ，現(xiàn)我們修改為 GND-Via，選項 Where The Frist Object Matches

2、 選Advaneed ( Query)， Full Query 輸入 IsVia (大小寫隨意)，Connect Style選 Direct Connect其他默認(rèn)設(shè)置，點(diǎn)擊下邊的priorities把GND-Via規(guī)則優(yōu)先級置最咼，(1為最咼，2次之)如下圖：-Design RulesName+ J* ElectricalPoliigorConnectNameGND-Via匚 ormfnentWhere The First Object MatchesOaiiOn臥ONet Class.； Layer二:Net and Lays.Advanced (Query)SMT MakPlane- _

3、 Power Plane Connect StlePlaneConnect- Power Plane Clearance_ PlaneCfoaranceQuery Helper.Query BuilderPolygon Connect SHImport Rules_ Polyjgonronnect if T e$tpointManuFacluringHigh Speedd J PlacementSignal IntegrityWhere The Second Object Matches OCX.； Net and LayerAdvanced (Query)Query Builder Full

4、 QueryConstraintsConnect Stylerelief connect 方回到PCB設(shè)計環(huán)境下進(jìn)行覆銅，覆銅網(wǎng)絡(luò)選GND，覆好銅以后對于網(wǎng)絡(luò)為 GND的Via (過孔)將為全覆銅的連接，而非默認(rèn)的式(熱焊盤方式)，由于規(guī)則是對過孔的全連接覆銅，所以對于焊盤的覆銅是熱焊盤方式連接方式，見下圖(左)：Direct 匚onnect vPrionitp EnabledNameScopeAttributesHOIHLdHGND-Via皿 AllStyle Direct Connect27PolygonConnectAll AlStyle 亠 Relief Connect Width =

5、 10mil Angle = 90 it Ertrie如果想過孔和焊盤多用熱焊盤方式，那在Full Query修改為IsVia or Is pad ，更新下剛才的覆銅，地焊盤也全連接了，如上圖(右)同樣也可 以 Full Query 為 Is pad， InNet( GND ) , InNet(GND ) And OnLayer( TopLayer ), InComponent(U1) , InComponent(U1 ) OR InComponent(U2 ) OR InComponent(U3 ) , innetclass(Power)等等1.InNet( GND )對于網(wǎng)絡(luò)名為 GND的

6、網(wǎng)絡(luò)進(jìn)行覆銅連接，覆銅連接規(guī)則采用lnNet( GND )的覆銅連接規(guī)則，注：InNet( X ),X為PCB中的網(wǎng)絡(luò)名，Conneet Style可全連接 或 熱焊盤 或 無連接 方式；熱焊盤方式還可設(shè)置2 , 4連接，45度，90度和連接線寬，下面的也類同；2.InNet(GND)And OnLayer(TopLayer)，對于位于TopLayer 層的GND網(wǎng)絡(luò)進(jìn)行的覆銅采用該覆銅連接規(guī)則，OnLayer(X),X為層名，層名稱修改可通過Desig nLayer Stack Man ager,雙擊層名稱修改。；3.InComponent(U1)，對于元件U1的覆銅采用該覆銅連接規(guī)則，U1

7、上有個X網(wǎng)絡(luò)，同時覆銅的網(wǎng)絡(luò)也為X,這樣改規(guī)則才有效果，例如U1上有個管腳連接到 GND網(wǎng)絡(luò)，同時覆銅網(wǎng)絡(luò)選GND,此時改規(guī)則才有效果；否則等于沒有這個規(guī)則，與不建立規(guī)則效果一樣；4.InComponent(U1)OR InComponent(U2)OR InComponent(U3)對于 元件 U1,U2,U3 采用該覆銅連接規(guī)則， 即 U1,U2,U3多采用改覆銅連接規(guī)則，關(guān)系是OR ,而非AND;innetclass(Power), Power類網(wǎng)絡(luò)的覆銅連接方式規(guī)則，DesignClasses創(chuàng)建一個規(guī)則類，類的方式有多種，網(wǎng)絡(luò)類，元件類，層類等。網(wǎng)絡(luò)類指向PCB中的網(wǎng)絡(luò)名，層類指向

8、PCB中的元件(焊位)，層類指向PCB中的層；例：innetclass(Power)，在net classes(網(wǎng)絡(luò)類)下新建一個規(guī)則(new rule )，同樣是右鍵增加，并改名為Power，選中這個網(wǎng)絡(luò)類規(guī)， 添加左邊的的網(wǎng)絡(luò)到右邊去，比如添加GND ,VCCINT ,VCC3.3,VCC1.2,VCCA,GNDA等這樣在多個多個網(wǎng)絡(luò)的不同覆銅就不用分別建立GND , VCCINT , VCC3.3 , VCC1.2 , VCCA , GNDA的覆銅連接規(guī)則，自需要建立一個網(wǎng)絡(luò)類覆銅連接規(guī)則即可，在覆銅的時候覆銅網(wǎng)絡(luò)連接到相應(yīng)的網(wǎng)絡(luò)即可；注意：所有上面的規(guī)則多要設(shè)置相應(yīng)的優(yōu)先級和新建規(guī)則，

9、新建規(guī)則的優(yōu)先級設(shè)為高，默認(rèn)規(guī)則的優(yōu)先級最低，其他優(yōu)先級看實(shí)際排列。所有選項 選 Where The Frist Object Matches選Advaneed (Query), Full Query輸入相應(yīng)的數(shù)據(jù)命令，對于相對簡單的類似只是網(wǎng)絡(luò)和層的覆銅連接InNet(GND) AndOnLayer(TopLayer)-頂層地網(wǎng)絡(luò)的覆銅連接方式，可選擇 The Frist Object Matches-Net and Layer，在里面的下拉框中選擇相應(yīng)的 Net和Layer后。Full Query框軟件會執(zhí)行填充數(shù)據(jù)，完成后 Apply OK回到PCB中(Full Query框中語法錯誤，

10、軟件會提示 錯誤，而填入一個不存在的層或網(wǎng)絡(luò)名則不會)，再在PCB進(jìn)行覆銅選擇相應(yīng)的覆銅網(wǎng)絡(luò)即可，覆銅間距默認(rèn)是10mil，如需特殊間距則需修改間距規(guī)則；高級間距規(guī)則比如覆銅間距二116mil，其他安全間距 8mil，過孔到過孔間距 100mil，焊盤到焊盤間距 lOOmil，焊盤到過孔間距l(xiāng)OOmil，頂層地覆銅0.8mm，頂層VCC3.3與VCC1.8覆銅間距0.5mm等Altium Designer的間距規(guī)則默認(rèn)為一個10mil間距，沒有區(qū)分焊盤到焊盤，過孔到過孔，走線到覆銅等的間距，想要高級規(guī)則，必須自己新建。在PCB設(shè)計環(huán)境下 DesignRulesElectricalClearan

11、ee ，同樣右鍵新建一個間距規(guī)則并重命名為 Poly，Where The First Object Matches 選 Adca need（ Query）， Full Query 輸入 in polygon，Con strai nts 把默認(rèn)的 10mil 修改為 20mil，優(yōu)先級 Poly 比默認(rèn)的的 Cleara nee 的 10mil 高，這2個間距規(guī)則共同構(gòu)成覆銅間距為20mil，其他間距例如走線到走線，走線到焊盤過孔間距為10mil的規(guī)則，如下圖：-Design Rules_ g ElectricaleaianciN arne PolyComment護(hù) Dea(c | 申摯 Sho

12、rt-Crc護(hù) ShorN -護(hù) Un-RouteP UnRo 瓷 UnConm + RoutingRule.Export.Export Rules.Import Rules.Where The First Object MatchesOaiiONetC Net ClassO LayerNet and Layer Advanced (Query)Query HeJper ,|Query BuilderConstraintsClerdncePrioriEnabled NameScopeAttributes1inpolygon - Allearance= 20|2ClearanceAllAllDe

13、a rance=WmilRule T ype:Full QueryinpolygonFull QueryAllDifferent Nek OnlyMinimum Clearance SOmil下2圖是過孔覆銅全連接 viaco nnect，默認(rèn)安全間距cleara nee 8mil，覆銅間距16mil規(guī)則的覆銅，in polygon是所有的覆銅，如果想要其他覆 銅間距，則需要在新建覆銅規(guī)則，比如VCC3.3覆銅0.5mm , VCC1.8覆銅間距0.6mm，其他覆銅0.4mm ;優(yōu)先級16mil的最低；覆一片銅到 VCC3.3網(wǎng)絡(luò)同時起名該覆銅為VCC3.3-ALL;覆一片銅到VCC1.8網(wǎng)絡(luò)

14、同時起名該覆銅為 VCC1.8-ALL;同樣要興建間距規(guī)則，見下面第3-6張圖：(+3 Design Rultt -J* Electrical -摯 Clearanceg ClearancePoJ-d Design Rules-二 Electrical-J* Clearance挈 dearmnee- Short-Circuit 羅 ShortCircuit-Un-RoUted Net UnRoutedNet ti-Connecied Pin*+ 亠 SMT* Mask-_ Plaiw- | Power Plane 匚onnect Style| PlaneCornect- | Power Pla

15、ne ClearancePlaneCleararice白fF?|/gon Connect StyleName viaconneutWhere The Frst Object Matches匚AllOrderNet 匚 lass: Layer；：rjet arid Layer 金 Advanced (QueryviaconnectCommentFull QueryisviaQuery Helper.Query Builder .Whier& The Second Object Matches All-OtJet(_) Net ClassO LayerNet arid Layer:; Adlvnc

16、ecl (Query) , _ Query Eiuilder ,Full QueryAllName PolyCommentvvi icrc 11 ic iriiriL Mijjn.u nauu m廠uii LucryinpolygonQ All 廣j njpkjNet ClassO LayerOet and Layer*) Advanced (Query)Query Helper ，Query Builder “*Full QueryAllTVI1 1 IDIURMLLJ ID為 AHL、 RLlpk Advanced (Query)CommentFull Queryinpo LygonQue

17、ry Helper.Query Builder .Where The Second Object MatchesDifferent Nets OnlyMinimurn Clearance 04rimO NetO Net Class(.)LayerNet and LayerFull QueryAllO Advanced (Query)bail血rConstraint-dDe$igri Rules匕亍 Electrical -護(hù) ClearanceVCC1.8-ALL f* VCC3MALLName ClearanceCommentClearance-亍 Shoit-Crcut狀 ShartCir

18、cuit- Un Pouted Nel 矛 UhRoutedNst g Un connected Pin + Routing+ SMT+ Mask-| PlaneDifferert Nets Clnly-M inimum Cleaance 0.254mmWhere The First Object MatchesAilNetNet ClassLayerQ1 Net and Layer O Advanced (Query)Full QueryAllQuery Builder Where The Second Object Matches AII Net 二、Net ClassOLayer O N

19、et and Layer.： Advanced (Query)ConstraintsQuery Guilder .Full QueryAll下圖是過孔到過孔的間距規(guī)則，Where The First Object Matches ,Where The Second Object Matches 的 FullQuery，只有這 2 個參數(shù)一個是 isvia ,另一個是ispad即可；如果一個是ispad另一個是isvia，那就是過孔到焊盤的間距；如果一個是ispad另一個是ispad,那就是焊盤到焊盤的間距；隨后填入具體的間距即可，Where The Seco nd Object Matches

20、 默認(rèn)是ALL ，修改他就是第一個和第二個間距規(guī)則，IsVia和ALL 就是Via到其他的間距規(guī)則，IsVia和IsVia就是過孔到過孔的間距規(guī)則；-Design Rules-十 Electrical-尹 Clearance j !療J* hols L1 -GND.ALLL4-GND_ALL尹 L3 Track_/ANAPolylAP Poly-L3 J* Poly LI J* Clearance-亍 ShortCrcut狀 ShortCircuit-Un Routed Net 滬 UnRoutedNet 群 Un-Connected Pin + Routing + JSMTN ame via

21、-to-viaCommerilvia-to-viaWhere The First Object MatchesoooNet ChssOLayer Net 目nd Layer Advanced (Query)Query Helper .Query Builder ,Where The Second Object Matches:./AllFull QueryisviaFull Queryisvia+ Mask- Plane-| Power Plans Conned StyleAareConnectI- Power Phne Clearance| PlaneClearance- Polygon C

22、onnect Se-_J Polvgon_Reief_BOTTOM| Poljgon_R elief_T 0 P PolygorLRelief .PolvgonConnectC Net ClassOLayerC Net and LayerAdvanced (Query)Constraints+ z T estpoint+ Mariufacturing+ .5High Speed過孔到過孔間距沒有至UQuery Helper.Query Builder .Deferent Nets Only-Minimum Clearance 2.54mm2.54mm的在線DRC檢查出來綠色顯示;注：設(shè)置小間距

23、管腳間距：一些FPGA芯片等很多焊盤間距多達(dá)到了0.2mm，默認(rèn)的10mil (0.254mm)間距顯然是沖突的，上述問題可以通過HasFootpri nt(PQ208)或 IsPad and In Compo nen t(U1);(IsPad and In Compo nent( JP4 ) or (IsPad and In Comp onent( JP3)HasFootprint(PQ208)，封裝為 PQ208 的元件；sPad and InComponent(U1)，元件 U1 的管腳間的間距；上面2個規(guī)則只是管腳間距，叢上面拉出來的線的間距是其他的規(guī)則值，當(dāng)然不能太大；比如上面的PQ

24、208焊盤0.3mm。焊盤間距0.2mm，布線0.2mm，那拉出來的線間距就是 0.4mm。如果把布線間距設(shè)為0.5mm,1mm，要么綠色，要么拉不出來；(IsPad and InComponent(JP4)or (IsPad and InComponent(JP3)，元件 JP3,JP4 的間距規(guī)則；見下面3張圖：- Design Rules-3* Electrical -g Clearance 寵 Clearance Polygon 富 Clearance_FPGA f Clearance+ 護(hù) Short-CicLiit-護(hù) Un-Routed Net UnRoiiedNef 計 Un-

25、Carmctad Pin+ h Routing+ *SMT+ Mask-Plane-| Power Plane Cannect StePlaneConnect- | Poi/ver Plane 匚learancePlaneClearance- | Polygon Connecl Stle PogcmConnectNme Clearance. FPGAWhere The Rrst Object MatchesOaiiO PJetO 函t ClassOLayer(_ Net end Layer(r?- Advanced (Query)+ 勿* T set point+M anufacturing+

26、 C High Speed* O Placement+ lSignallritegritv-zJ Design Rule-尹 Electrical-J* Clearance 匸 Clearance_PQ208 尹 Clearance_ Polygon g Clearance_FPGA 矛 Clearance* 尹 ShortTircuit-亍 Un-RoUted Net十 UnRoutedNet 尹 Un-Connected Pin+ Routing+，SMT十 Mask-_ Plane- Power Plane Connect StylePlaneConnect- | Power Plane

27、 ClearancePlaneCleatance- Polygon Connect StylePolgonConnect+ T estpoint+ r MonufEcturing+ 匸High Speed+ O PlacBmert+ |h-Signal Integnt-Design Rules-J* Electrical -了 ClearanceJ* Clearance J* BmilDilfefeht Nsts On-Minimum Clearance 5milCommentQuery Helper.,Query Bunder .V/here The Second Object Mdtche

28、s AllC1 Met(5 IMet ClassO LayerL ； l*4et and Layer(._ Advanced (Query)Query BuilderCcmslraintsDifferent Nets OhlyName ClearancE_PQ208Where The First Object MatchesOaIIQNetO Net ClassLayerO IMet and Layer Advanced (Query)Unique ID GY TVFull QueryIsPad and InComponent(1U11)Full QueryAllMinimum Clearan

29、ce 0,2mm|L DmmentQuery HelperQuery BuHder 1Where The Second Object MatchesO FJet nd LayerC) Advanced (Query)Con規(guī)怕inkN ame ClearanceUniqueFull QueryHasFootprint(1PQ2O81)Full QueryQuery Suider Where The First Object MatchesOaiiONetO Net ClassO LayerNet and Layer/. Advanced (Query)Different Nets OnlyMi

30、nimum Cleafance 0.2mm|CommentUnique ID HFWKJTMQuery Helper Full QueryflsPadandInComponent(1JP41)orIsPstdandInComponent(fJP31)orIsPadandInCortiponent (1 u2 1 )or(IsPadandInCcinpcnnt ( 1 j p5 1 )or(IsPadandInCcmponent(1 jp2 1 )Query Builder Net and LayerQuery Helper . Net and Layer：_.： Advanced (Query

31、)Query Builder CZ1R2Full QueryHasPad(1free-HOLE)Full QueryAllConstrairtsDifferent Neb 0訕Minimum Clearance 10OFnilF圖為一個在toplayer層覆銅名為5VANA的間距規(guī)則，當(dāng)然toplayer可以換成其他層，5VANA可以換成其他覆銅的名稱;-Design Rule-Elaclrcal-尹earance 書 top_5VANA P VCC1 8 ALL J* VCC3 3ALL 當(dāng) OtherPoly f ClearanCB-J* Short-Circuit亍 ShorOcuit-

32、詈 Uin-Routed NetUnRoUedJel試 Un-Corinected Pin+ Routing+ SMT+ Masktj L Plane- Power Plane Connect Style| PlaneConnect- Power Plane Clearance_ PlaneClearance-| Polygon Connect Sfyle_ yiaconnectPolygoriConnect+ Z T estpoint+ Manufacturing+ cH：! High Speed+ U Placement+ | li Signal IntegrityNme lop_3VAN

33、ACommentUnique IDWhere The First Object MatchesooooClassLayer O Net and Layer .： Advanced (Query)Query Helper .I Quer/Builder |Where The Second Object Matches Net匚:,Net ClassO Layer(j Net and Layer(.1 Advanced (Query)ConstraintsLDQuery Builder .,Full QueryOnLayer(1 toplayer 1) ANDInNfledPolygon (5VA

34、NA)Different Nets Only)-Minimum Clearance 0.4mmF圖為DM到DP網(wǎng)絡(luò)間距為20mil的間距規(guī)則:-|d Design Rulej-羅 Electrical-計 Clearance 亍 DP DM 卜 8mil-g Short-Circuit尹 ShodCircuit-君 Un-Routed Net UnRoutedNelT UnConnected Pin + 上 Routing+1SMTNameDP-DMCommentWhere The First Object MatchesLayer.： Met and LayerO Advanced (Que

35、ry)Query Builder.FuO QueryInNet ( lDHl )+ Mask-| Plaine- Power Hare Connect Style.PhneConnect- Power Flare ClearancePlaneClearance-_ Polygon Connect Style PoliigorConnect+ L Te就point+ 號Maniiacturing* ； _3 High Speed+ Jj Placement+ n Signal IntegrityWhere The 5econd Object Matches.Dierent Nets Only-M

36、ininun Clearance 20milCommentWhere The First Object MatchesO(*) NetO Net ClassQ) LayerO Net 呂nd LayerQ Advanced (Query)Query BuilderFiji QueryMSCLMInNet ( 1 MSCLK11 )Plane一Po/rer Plane Conned StylePlansConnect$sPower Plane CleganesPlaneOearancePolygon Ccnnecl Style PolgonCoinnect+ / Testpoint+ y Man

37、ufacturingWhere The Second object MatchesCon$trainh+ ； High Speed+ 廿 Phcerrient+ | |j Signal IntsrityDifferent NeU OnlyMinimum Clearance 1 Snil高級線寬規(guī)則設(shè)置 GND 網(wǎng)絡(luò) 30mil , VCC 網(wǎng)絡(luò)線寬 20mil，布線時按 TAB ,Track Width Mode 選 Rule Preferred ;-Design Rules 十計 E lectrical-Routing-WidthName W.VCC|W VCC成 V/GND；戈 Width

38、-Routing Topology 芒 AoutingT 口 polow-氏 Routing Priofity 気 Routin尹riority-Routing Lasers RoutingLayers-Routing Corners 衛(wèi) RoutingCarners-Routing Via Style二 AoutingVias+ Fanout Control-J Differential Pairs Routing _/= D if fPairsR outing+ SMT+ Mask-_J Plane-Power Plaie Connect StylePlane Connect匚PnuiiF

39、 PlAftPtInnirni鬥嚴(yán)a匚 om meritConbaintsPreferred Width OmilIMin Width WmilMaw Width OmilI I Characteristic ImpedaM Layers in layertack oAttributes on LtyeiMin Width Prewired Size10hiil20mil10nil20milFull QueryInNet(1VCC1)Laer Stack ReferenceWax Width Name11.lOOmil T opLayer0lOOmil BottomLayer1hel Desi

40、gn Rules* g Electrical-j Routing-WidthflW.VCC；iName WGNDCommentWGNDWidth-上 Routing TopologiRoutingT opdagy-Routing Priori)丈 RoutingPrierity-Routing Layers jRoutingLayers-Routing CornersRoutingCoineis-Routing Via SteRtMjtinsjViaj+ 衛(wèi) Fanout Control-幾 Differentid Pairs RoutingDiffPairsR outing+ 7MT+ Mask-_| Plaine- Power Plane Connect Ste.PlaneConnect- PrtiAJpr Phnft ClftflrAnnF竝 Routing-拓 W