(完整word版)集成電路CAD復(fù)習(xí)例題+解析.doc

1、1、 3-8 譯碼器Index 方式module decoder_index (in1, out1);parameter N = 8;parameter log2N = 3;input log2N-1:0 in1;output N-1:0 out1;reg N-1:0 out1;always (in1)beginout1 = 0;out1in1 = 1 b1;endEndmoduleLOOP方式module decoder38_loop (in1, out1);parameter N = 8;parameter log2N = 3;input log2N-1:0 in1;output N-1:

2、0 out1;reg N-1:0 out1;integer i;always (in1)beginfor(i=0;iN;i=i+1)out1i = (in1 = i);end2、 8-3 優(yōu)先編碼器module priority_low_high (A, P);parameter N = 8;parameter log2N = 3;input 0:N-1 A; /Input Vectoroutput log2N-1:0 P; / High Priority Indexreg log2N-1:0 P;function log2N-1:0 priority;input 0:N-1 A;intege

3、r I;beginpriority = 3 b0;for (I=0; IN; I=I+1)if (AI)priority = 7-I;/ Override previous indexendendfunctionalways (A)P = priority(A);endmodule另一種：module code8_3(in,out)input 7:0 in; output 2:0 out; wire 7:0 in; reg 2:0 out; always (in) beginif(in7=1) out=3 111;else if(in6=1) out=3 b110; else if(in5=1

4、) out=3 101;else if(in4=1) out=3 b100;else if(in3=1) out=3b011;else if(in2=1) out=3 b010; else if(in1=1) out=3 b001;else if(in0=1) out=3 b000;default:out=3 bx; endendmodule3、奇偶校驗(yàn)位產(chǎn)生器module parity(even_bit,odd_bit,input_bus);output even_bit,odd_bit;input7:0 input_bus;assign even_bit = input_bus;assig

5、n odd_bit = even_bit;/ 產(chǎn)生偶校驗(yàn)位/ 產(chǎn)生奇校驗(yàn)位endmodule4、 4 選 1 數(shù)據(jù)選擇器第一種方法module mux(d1,d2,d3,d4,se1,se2,dout);input d1;input d2;input d3;input d4;input se1;input se2;output dout;reg dout;always (d1 or d2 or d3 or d4 or se1 or se2)case(se1,se2)2b00 : dout=d1;2b01 : dout=d2;2b10 : dout=d3;2b11 : dout=d4;endca

6、seendmodule第二種方法module mux(d1,d2,d3,d4,se1,se2,dout);input d1;input d2;input d3;input d4;input se1;input se2;output dout;reg dout;always (d1 or d2 or d3 or d4 or se1 or se2)if (!se1)beginif (!se2)dout = d1;elsedout = d2;endelse beginif (!se2)dout = d3;elsedout = d4;endendmodule第三種方法module se(d1,d2,d

7、3,d4,se1,se2,dout);input d1;input d2;input d3;input d4;input se1;input se2;output dout;reg dout;always (d1 or d2 or d3 or d4 or se1 or se2)assign dout=se1?se2?d4:d3:se2?d2:d1;endmodule第四種方法module mux4_1(out,in0,in1,in2,in3,sel);output out;input in0,in1,in2,in3;input1:0 sel;reg out;always (in0 or in1

8、 or in2 or in3 or sel) /敏感信號列表case(sel)2b00: out=in0;2b01: out=in1;2b10: out=in2;2b11: out=in3;default: out=2bx;endcaseendmodule5、 4位全加器及 4位全加器的仿真程序module adder4(cout,sum,ina,inb,cin);output3:0 sum;output cout;input3:0 ina,inb;input cin;assign cout,sum=ina+inb+cin;Endmodule第二種：module adder_4bit(s,co

9、,a,b,ci);/4位全加器/output3:0 s;output co;input3:0 a,b;input ci;f_adder f0(a0,b0,ci,s0,ci1);f_adder f1(a1,b1,ci1,s1,ci2);f_adder f2(a2,b2,ci2,s2,ci3);f_adder f3(a3,b3,ci3,s3,co);endmodulemodule f_adder(ain,bin,cin,sum,cout);/1位全加器/output sum,cout;input ain,bin,cin;wire d,e,f;h_adder(ain,bin,e,d);h_adder

10、(e,cin,sum,f);or(cout,d,f);endmodulemodule h_adder(a,b,so,co);/ 半加器/input a,b;output so,co;assign so = a b;assign co = a & b;Endmodule4 位全加器的仿真程序timescale 1ns/1nsinclude adder4.vmodule adder_tp;reg3:0 a,b;/ 測試模塊的名字/ 測試輸入信號定義為reg 型reg cin;wire3:0 sum;/ 測試輸出信號定義為wire型wire cout;integer i,j;adder4 adder

11、(sum,cout,a,b,cin);/ 調(diào)用測試對象always #cin=cin;/設(shè)定cin 的取值initialbegina=0;b=0;cin=0;for(i=1;i16;i=i+1)#10a=i;/ 設(shè)定a 的取值endinitialbeginfor(j=1;j16;j=j+1)#10b=j;/設(shè)定b的取值endinitial/ 定義結(jié)果顯示格式begin$monitor($time,%d + %d + %b=%b,%d,a,b,cin,cout,sum); #160 $finish;endendmodule6、帶同步清0、同步置1 的 D 觸發(fā)器moduled_ff_1(CLK,

12、 RSTn, clr, D, Q, en);inputCLK,RSTn,clr;inputD,en;outputQ;regQ;always(posedgeCLK)beginif(RSTn)beginQ = 1b1;endelse beginif(clr)begin Q = 1b1;endelse beginif(en) beginQ=Dendelse;beginQ=Q;endendendendmodule7、帶異步清0、異步置1 的 JK 觸發(fā)器module JK_FF(CLK,J,K,Q,RS,SET);input CLK,J,K,SET,RS; output Q; reg Q;always

13、 (posedge CLK or negedge RS or negedge SET)beginif(!RS) Q = 1b0;else if(!SET) Q = 1b1;else case(J,K)2b00 : Q = Q;2b01 : Q = 1b0;2b10 : Q = 1b1;2b11 : Q = Q;default: Q= 1bx;endcaseendendmodule8、 8 位數(shù)據(jù)鎖存器modulelatch_8(qout,data,clk);output7:0 qout;input7:0 data;input clk;reg7:0 qout;always (clk or dat

14、a)beginif(clk)qout=data;endendmodule9、 同步置數(shù)、同步清零的8 位二進(jìn)制計(jì)數(shù)器module count(out,data,load,reset,clk);output7:0 out;input7:0 data;input load,clk,reset;reg7:0 out;always (posedge clk)/clkbeginif (!reset)out = 8h00;/ 同步清 0，低電平有效else if (load)out = data;/ 同步預(yù)置elseout = out + 1;/ 計(jì)數(shù)上升沿觸發(fā)endendmodule10、異步清零、同步

15、置數(shù)的1 位十進(jìn)制計(jì)數(shù)器module count10(out,data,load,reset,clk);output3:0 out;input3:0 data;input load,clk,reset;reg3:0 out;always (posedge clk or negedge reset)beginif (!reset)out = 8h00;/ 同步清 0，低電平有效else if (load)out = data;/ 同步預(yù)置else if (out 9)out = out + 1;/計(jì)數(shù)else/clk上升沿觸發(fā)out = 0;endendmodule11、 4 位串并轉(zhuǎn)換器mod

16、ule pal_serial_4(clk,rst,load,din,dout);/ 四位并串轉(zhuǎn)換程序input clk,rst,load;input3:0 din;output dout;reg3:0 databuff;always (posedge clk or negedge rst or posedge load)beginif(!rst) databuff=4b0;else if(load) databuff=din;else /databuff=databuff2:0,1b0;databuff=databuff1;/將寄存器內(nèi)的值左移，依次讀出endassign dout=datab

17、uff3;endmodulemodule serial_pal_4(clk,en,rst,/四位串并轉(zhuǎn)換程序cin,cout);input cin,clk,en,rst;output3:0 cout;reg3:0 cout;always (posedge clk or negedge rst)beginif(!rst) cout=4b0;else if(en)cout=cout2:0,cin;else cout=cout;endendmodule另一種：module shift(nreset,clk,en,in,out);inputnreset,clk,en,in;output 3:0 out

18、;reg 1:0 count;/ 移位計(jì)數(shù)，控制并行數(shù)據(jù)更新，這里是4bit 并行數(shù)據(jù)reg 3:0 data;reg 3:0 out;always(posedge clk or negedge nreset)beginif(nreset)count = 2b00;else if(en)count = count + 2b01;endalways(posedge clk or negedge nreset)beginif(nreset)data = 4b0000;eale if(en)data = data2:0,in;end/并行輸出always(posedge clk or negedge

19、 nreset)beginif(nreset)out = 4b0000;else if(en & (count=2b11)out = data;endendmodule12、模為 60 的 BCD 碼加法計(jì)數(shù)器module count60(qout,cout,data,load,cin,reset,clk);output7:0 qout;output cout;input7:0 data;input load,cin,clk,reset;reg7:0 qout;endmodulealways (posedge clk)beginif (reset)qout=0;/同步復(fù)位/clk上升沿時刻計(jì)數(shù)

20、elseif(load)qout=data;/ 同步置數(shù)elseif(cin)beginif(qout3:0=9)/ 低位是否為9，是則beginqout3:0=0;/ 回0，并判斷高位是否為5if (qout7:4=5)qout7:4=0;elseqout7:4=qout7:4+1;/ 高位不為5，則加1endelse/低位不為9，則加1qout3:0=qout3:0+1;endendendassign cout=(qout=8 h9)&cin)?1:0;/ 產(chǎn)生進(jìn)位輸出信號endmodule13、 BCD 碼七段數(shù)碼管顯示譯碼器module decode47(a,b,c,d,e,f,g,D

21、3,D2,D1,D0);output a,b,c,d,e,f,g;input D3,D2,D1,D0;/ 輸入的4 位BCD碼reg a,b,c,d,e,f,g;always (D3 or D2 or D1 or D0)begincase(D3,D2,D1,D0)/用case語句進(jìn)行譯碼4d0: a,b,c,d,e,f,g=7b1111110;4d1: a,b,c,d,e,f,g=7b0110000;4d2: a,b,c,d,e,f,g=7b1101101;4d3: a,b,c,d,e,f,g=7b1111001;4d4: a,b,c,d,e,f,g=7b0110011;4d5: a,b,c,

22、d,e,f,g=7b1011011;4d6: a,b,c,d,e,f,g=7b1011111;4d7: a,b,c,d,e,f,g=7b1110000;4d8: a,b,c,d,e,f,g=7b1111111;4d9: a,b,c,d,e,f,g=7b1111011;default: a,b,c,d,e,f,g=7bx;endcaseendendmodule14、七人投票表決器，4 人同意即為通過，反之不通過。module voter7(pass,vote);output pass;input6:0 vote;reg2:0 sum;integer i;reg pass;always (vote

23、)beginsum=0;for(i=0;i=6;i=i+1)/for語句if(votei) sum=sum+1;if(sum2)pass=1;/ 若超過4 人贊成，則pass=1elsepass=0;endendmodule15、設(shè)計(jì)一個簡單的狀態(tài)機(jī)，功能是檢測一個5 位二進(jìn)制序列“10010”module VrSMex( CLOCK, X, Z);input CLOCK, X;output Z;reg Z;reg 2:0 Sreg, Snext;parameter 2:0 A = 3b000,B = 3b001,C = 3b010,D = 3b011,E = 3b100,F = 3b101;

24、always (posedge CLOCK)Sreg = Snext;always (X, Sreg) begincase (Sreg)A:if(X=0)Snext = A;elseSnext = B;B:if(X=0)Snext = C;elseSnext = B;C:if(X=0)Snext = D;elseSnext = B;D:if(X=0)Snext = A;elseSnext = E;E:if(X=0)Snext = F;elseSnext = B;F:if(X=0)Snext = A;elseSnext = B;default Snext = A;endcaseendalways (Sreg)case (Sreg)A,B,C,D,E:Z=0;F:Z=1;default