播放音樂和頻率計設(shè)計

1、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY fengping ISPORT(clk:IN STD_LOGIC;clk4hz:OUTSTD_LOGIC;clk1mhz:OUTSTD_LOGIC);END fengping;ARCHITECTURE ONE OF fengping ISsignal count:integer;signal count1:integer;beginprocess(clk)begin if(clkeve

2、nt and clk=1) then if(count1=12500000)thencount1=0; elsecount1=count1+1; if count16250000 then clk4hz=0; else clk4hz=1; end if; end if;end if;end process;process(clk)begin if(clkevent and clk=1) then if(count=50)thencount=0; elsecount=count+1; if count25 thenclk1mhz=0; elseclk1mhz=1; end if; end if;

3、end if;end process; end;library ieee;use ieee.std_logic_1164.all;entity notetabs isport( clk : in std_logic; toneindex : out integer range 0 to 15);end notetabs;architecture behav of notetabs issignal counter : integer range 0 to 138;begincnt8: process(clk,counter)beginif counter=138 then counter=0;

4、elsif clkevent and clk=1 then countertoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindexto

5、neindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextonei

6、ndextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneinde

7、xtoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindexto

8、neindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindextoneindexnull;end case;end process;end behav;library ieee;use ieee.std_logic_1164.all;entity speaker isport( clk : in std_logic; tone : in integer range 0 to 16#7ff#; -2047; spks : out std_logic);end speaker;architecture

9、behav of speaker issignal fullspks : std_logic;begingenspks : process(clk,tone) -clk=1MHZ;variable count11 : integer range 0 to 16#7ff#; -2047;beginif clkevent and clk=1 thenif count11=16#7ff# then -b111,1111,1111;count11:=tone;fullspks=1;else count11:=count11+1;fullspks=0;end if;end if;end process;

10、delay: process(fullspks) -fullspks=488.2815HZ;variable count2 : std_logic;beginif fullspksevent and fullspks=1 thencount2:=not count2;if count2=1 thenspks=1;elsespkstone=2047; codetone=773; codetone=912; codetone=1036; codetone=1197; codetone=1290; codetone=1372; codetone=1410; codetone=1480; codeto

11、ne=1542; codetone=1622; codetone=1668; codetone=1728; codenull;end case;end process;end behav;頻率計library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity testctl isport( clk : in std_logic; tsten : out std_logic; clr_cnt : out std_logic; load : out std_logic);end testctl;archi

12、tecture behav of testctl issignal div2clk : std_logic;beginprocess(clk)beginif(clkevent and clk=1) then div2clk=not div2clk;end if;end process;process(clk,div2clk)beginif(clk=0 and div2clk=0) thenclr_cnt=1;elseclr_cnt=0;end if;end process;load=not div2clk;tsten=div2clk;end behav; library ieee;use ie

13、ee.std_logic_1164.all;entity reg32b isport( load : in std_logic; din : in std_logic_vector(31 downto 0); dout :out std_logic_vector(31 downto 0);end reg32b;architecture behav of reg32b isbeginprocess(load,din)beginif(loadevent and load=1) thendout=din;end if;end process;end behav;library ieee;use ie

14、ee.std_logic_1164.all;entity cnt10 isport(clk: in std_logic; clr: in std_logic; ena: in std_logic; cq : out integer range 0 to 15; carry_out: out std_logic);end cnt10;architecture behav of cnt10 issignal cqi: integer range 0 to 15;beginprocess(clr,clk,ena)beginif(clr=1) then cqi=0;elsif(clkevent and

15、 clk=1) thenif(ena=1) thenif(cqi9) then cqi=cqi+1;else cqi=0;end if;end if;end if;end process;process(cqi)beginif(cqi=9) thencarry_out=1;elsecarry_out=0;end if;end process;cq=cqi;end behav;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity seltime isport( clk : in std_lo

16、gic; rst : in std_logic; din : in std_logic_vector(31 downto 0); daout: out std_logic_vector(3 downto 0); sel : out std_logic_vector(2 downto 0);end seltime;architecture behav of seltime issignal sec : std_logic_vector(2 downto 0);beginprocess(rst,clk)beginif(rst=0) thensec=000;elsif(clkevent and cl

17、k=1) then if(sec=111) then sec=000;else secdaoutdaoutdaoutdaoutdaoutdaoutdaoutdaoutdaout=XXXX;end case;end process;seldig_rdig_rdig_rdig_rdig_rdig_rdig_rdig_r=01111111;-選擇第八個數(shù)碼管顯示END CASE;END PROCESS;dig=dig_r;end one;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity di

18、v_f isport(clk :in std_logic; onehz_out :out std_logic; five_h_hz_out :out std_logic; one_h_khz_out :out std_logic; one_M_hz_out :out std_logic; five_M_hz_out:out std_logic; two_h_hz_out:out std_logic; fifty_hz_out:out std_logic; ten_hz_out:out std_logic; twnty_f_hz_out:out std_logic; zeros_one_hz_o

19、ut:out std_logic; one_h_hz_out:out std_logic; five_h_khz_out :out std_logic); end div_f;architecture behave of div_f isbegin p1:process(clk)variable cnt:integer range 0 to 24999999; -分頻系數(shù)為24999999variable ff:std_logic;beginif clkevent and clk=1 thenif cnt24999999 thencnt:=cnt+1;elsecnt:=0;ff:=not ff

20、; -反向end if;end if;onehz_out=ff;end process p1;p2:process(clk)variable cnn:integer range 0 to 49999; -分頻系數(shù)為12499999variable dd:std_logic;beginif clkevent and clk=1 thenif cnn49999 thencnn:=cnn+1;elsecnn:=0;dd:=not dd; -反向end if;end if;five_h_hz_out =dd;end process p2;p3:process(clk)variable cnn1:int

21、eger range 0 to 24999; -分頻系數(shù)為24999variable dd1:std_logic;beginif clkevent and clk=1 thenif cnn124999 thencnn1:=cnn1+1;elsecnn1:=0;dd1:=not dd1; -反向end if;end if;one_h_khz_out =dd1;end process p3;p4:process(clk)variable cnn2:integer range 0 to 24; -分頻系數(shù)為24variable dd2:std_logic;beginif clkevent and c

22、lk=1 thenif cnn224 thencnn2:=cnn2+1;elsecnn2:=0;dd2:=not dd2; -反向end if;end if;one_M_hz_out =dd2;end process p4;p5:process(clk)variable cnn3:integer range 0 to 4999; -分頻系數(shù)為499999variable dd3:std_logic;beginif clkevent and clk=1 thenif cnn34999 thencnn3:=cnn3+1;elsecnn3:=0;dd3:=not dd3; -反向end if;end

23、 if;five_h_khz_out =dd3;end process p5;p6:process(clk)variable cnn4:integer range 0 to 4; -分頻系數(shù)為5variable dd4:std_logic;beginif clkevent and clk=1 thenif cnn44 thencnn4:=cnn4+1;elsecnn4:=0;dd4:=not dd4; -反向end if;end if;five_M_hz_out =dd4;end process p6;p7:process(clk)variable cnn5:integer range 0 t

24、o 124999; -分頻系數(shù)為125000variable dd5:std_logic;beginif clkevent and clk=1 thenif cnn5124999 thencnn5:=cnn5+1;elsecnn5:=0;dd5:=not dd5; -反向end if;end if;two_h_hz_out =dd5;end process p7;p8:process(clk)variable cnn6:integer range 0 to 499999; -分頻系數(shù)為500000variable dd6:std_logic;beginif clkevent and clk=1 thenif cnn6499999 thencnn6:=cnn6+1;elsecnn6:=0;dd6:=not dd6; -反向end if;end if;fifty_hz_out =dd6;end process p8;p9:process(clk)variable cnn7:integer range 0 to 2499999; -分頻系數(shù)為500000variable dd7:std_logic;beginif clkevent and clk=1 thenif cnn