數(shù)電課程設(shè)計競賽搶答器_第1頁
數(shù)電課程設(shè)計競賽搶答器_第2頁
數(shù)電課程設(shè)計競賽搶答器_第3頁
數(shù)電課程設(shè)計競賽搶答器_第4頁
數(shù)電課程設(shè)計競賽搶答器_第5頁
已閱讀5頁,還剩12頁未讀, 繼續(xù)免費閱讀

下載本文檔

版權(quán)說明:本文檔由用戶提供并上傳,收益歸屬內(nèi)容提供方,若內(nèi)容存在侵權(quán),請進行舉報或認領(lǐng)

文檔簡介

1、 數(shù)電課程設(shè)計實驗報告 課題:競賽搶答器 學院:電氣與信息工程學院 姓名:班級:電子信息工程1001班 目錄一、課程設(shè)計的要求及目的- 1 -二、設(shè)計的功能要求- 2 -三、設(shè)計思路框圖- 3 -四、vhdl程序- 4 -1、鍵盤轉(zhuǎn)按鍵模塊- 4 -2、顯示模塊- 6 -3、主模塊- 9 -五、電路連接圖- 14 -六、心得體會- 14 -一、課程設(shè)計的要求及目的1了解電子設(shè)計的具體流程和方法。 2. 掌握電子設(shè)計的基本要求,能夠運用所學的知識解決生活中的一些問題。 3. 初步掌握vhdl語言編程,并設(shè)計出一個有意義的小型系統(tǒng)。 4. 掌握altium designer 6.9軟件的應用,并且

2、了解相關(guān)硬件的組成和功能。 5. 用eda(electronic design automation)或者原理圖完成一個課題的設(shè)計,并達到相應的功能要求。 二、設(shè)計的功能要求 在許多比賽活動中,為了準確、公正、直觀地判斷出第一搶答者,通常設(shè)置一臺搶答器,通過數(shù)顯、燈光及音響等各種手段批示出第一搶答者。同時,還可以設(shè)置計分、犯規(guī)及獎懲記錄等各種功能。本設(shè)計利用eda技術(shù),可容納8組參賽,每組設(shè)置一個按鈕供參賽者搶答使用。主持人按下開始按鍵后,10s倒計時開始,當一組搶答器按下后,1602lcd顯示搶答的組別。由于搶答器具有第一信號鑒別和鎖存功能使其余的組就搶答無效,搶答的組回答問題后由主持人進行

3、加減分,然后主持人按復位鍵后繼續(xù)進行搶答。1、在1602lcd屏幕上顯示所需組別及分數(shù);2、考慮到有選手犯規(guī),在主持人未按下開始鍵但是已經(jīng)有組別按下?lián)尨疰I時會在屏幕顯示該組別犯規(guī)(fg),并由主持人手動減分; 3、按下開始鍵后,有10s的時間供選手們搶答,如果30s后仍無人搶答,則蜂鳴器報警,并在屏幕上顯示超時(cs);4、每個組別設(shè)置的初始分數(shù)為0分,加分上限為9分; 5、能實現(xiàn)系統(tǒng)手動復位,復位后回到初始狀態(tài),并等待主持人按下開始鍵。三、設(shè)計思路框圖譯碼顯示譯碼優(yōu)先編碼 搶答按鈕控制模塊主持人控制開關(guān)顯示模塊定時模塊秒脈沖產(chǎn)生四、vhdl程序1、鍵盤轉(zhuǎn)按鍵模塊library ieee;us

4、e ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity padtokey is port ( cpin,r,validkey :in std_logic; key :in std_logic_vector(3 downto 0); keyout: out std_logic_vector(15 downto 0); clk_1mhz,rst: out std_logic );end entity ;architecture jgt of padtokey is s

5、ignal ctcp: integer range 0 to 5; signal cpo :std_logic:='0' signal ctcpo :integer range 0 to 4999; type states is (s0,s1,s2); signal s: states;beginprocess(cpin)beginif cpin='1' and cpin 'event then if ctcp=5 then cpo <= not cpo; ctcp<=0; else ctcp<=ctcp+1; end if;end i

6、f;end process;process(cpo,r)beginclk_1mhz<=cpo;if r='1' then rst<='0's<=s0;ctcpo<=0; keyout<="0000000000000000"elsif cpo='1' and cpo 'event then if ctcpo /= 4999 then ctcpo<=ctcpo+1; else ctcpo<=0; case s is when s0 =>rst<='0'

7、if validkey='1' then s<=s1; case key is when "0000"=>keyout<="0000000000000001" when "0001"=>keyout<="0000000000000010" when "0010"=>keyout<="0000000000000100" when "0011"=>keyout<="00000000

8、00001000" when "0100"=>keyout<="0000000000010000" when "0101"=>keyout<="0000000000100000" when "0110"=>keyout<="0000000001000000" when "0111"=>keyout<="0000000010000000" when "1000"

9、=>keyout<="0000000100000000" when "1001"=>keyout<="0000001000000000" when "1010"=>keyout<="0000010000000000" when "1011"=>keyout<="0000100000000000" when "1100"=>keyout<="00010000000000

10、00" when "1101"=>keyout<="0010000000000000" when "1110"=>keyout<="0100000000000000" when "1111"=>keyout<="1000000000000000" when others=>null; end case; else s<=s0;keyout<="0000000000000000" end if;

11、 when s1=>rst<='1's<=s2; when s2=>rst<='0's<=s0; when others=> null; end case; end if;end if;end process; end architecture jgt;此模塊使用狀態(tài)機將鍵盤的16個按鍵轉(zhuǎn)換為16個按鍵信號。2、顯示模塊library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity qdqlcd is port (cpin,r

12、,busy :in std_logic; fs1,fs2,fs3,fs4,fs5,fs6,fs7,fs8,tm :in std_logic_vector(7 downto 0); zb : in std_logic_vector(3 downto 0); teshu : in std_logic_vector(1 downto 0); clk,rst,strobe,outline : out std_logic; data : out std_logic_vector(7 downto 0); addr : out std_logic_vector(3 downto 0) );end enti

13、ty ;architecture jgt of qdqlcd is type states is (s0,s1,s2,s3,s4); signal s: states; signal lcdpt : integer range 0 to 27; signal cpct : integer range 0 to 65535; signal cp: std_logic; -signal ascew,ascsn : std_logic_vector(7 downto 0);beginprocess(cpin,r)beginclk<=cpin;if r='1' then cpct

14、<=65535;elsif cpin='1' and cpin 'event then if cpct=0 then cpct<=65535;cp<=not cp; else cpct<=cpct-1; end if;end if;end process; -·ÖƵΪ500usÖÜÆÚ-Ö÷½ø³Ì£ºÄâ²ÉÓ&#

15、195;500usʱÖÓ£¬¼´ÔÚ500usºóÍê³É״̬ת»»£¬ÐÞ¸ÄlcdptÖ¸Õë-s0:³õʼ״̬,ÔÚr=1Ê

16、77;£¬´¦ÓÚs0״̬,lcdpt=0- Á÷³Ì£º Êä³örst=1, תs1-s1:Êä³örst=0;ÅжÏbusy=0? :y: lcdpt+1;lcdptµ½¹Ì¶¨×îºó

17、£¿:n: ->s2 - :y: תs3- ;n; null-s2:¸ø³östrobeÐźš£×ªs1-s1,s2Íê³É³õʼ»¯¹Ì¶¨ÏÔʾµÄ¹¦ÄÜprocess(cp,r

18、)beginif r='1' then s<=s0;lcdpt<=0;rst<='1'elsif cp='1' and cp 'event then case s is when s0=> s<=s1;lcdpt<=0;rst<='1' when s1=> rst<='0'strobe<='0' if busy='0' then lcdpt<=lcdpt+1; if lcdpt=7 then s<=s3;

19、 else s<=s2; end if; end if; when s2=> s<=s1;strobe<='1' -s3s4Íê³ÉɨÃèÏÔʾ¹¦ÄÜ-s3:busy=0? :y: lcdptÑ­»·+1 £¬×ªs4-s4:¸ø³östrobeÐÅ&#

20、186;Å£¬×ªs3 when s3=> strobe<='0' if busy='0' then if lcdpt=27 then lcdpt<=7; else lcdpt<=lcdpt+1; end if; s<=s4; end if; when s4=> strobe<='1's<=s3; when others=> null; end case;end if; end process;-Ñ¡Ôñ

21、Êä³ö½ø³Ì(lcdpt)-lcdpt=0,null- =16 ÏÔʾ zb: tm: e 45h,5 w57h,6 s53h,9 n4eh,10process(lcdpt)begincase lcdpt iswhen 0 => null;when 1=> data<="01011010"addr<="1001"outline<='1' -zwhen 2=> data<=&

22、quot;01000010"addr<="1010"outline<='1' -bwhen 3=> data<="00111010"addr<="0100"outline<='1' -:when 4=> data<="01010100"addr<="0010"outline<='1' -twhen 5=> data<="01001101"addr&

23、lt;="0011"outline<='1' -mwhen 6=> data<="00111010"addr<="1011"outline<='1' -:-lcdpt=722 ÏÔʾfs1fs8-lcdpt=2325 ÏÔʾzb/tmwhen 7=>data<="0011"&fs1(7 downto 4);addr<="0000&quo

24、t;outline<='0'when 8=>data<="0011"&fs1(3 downto 0);addr<="0001"outline<='0'when 9=>data<="0011"&fs2(7 downto 4);addr<="0010"outline<='0'when 10=>data<="0011"&fs2(3 downto 0);addr<

25、;="0011"outline<='0'when 11=>data<="0011"&fs3(7 downto 4);addr<="0100"outline<='0'when 12=>data<="0011"&fs3(3 downto 0);addr<="0101"outline<='0'when 13=>data<="0011"&fs4(7

26、 downto 4);addr<="0110"outline<='0'when 14=>data<="0011"&fs4(3 downto 0);addr<="0111"outline<='0'when 15=>data<="0011"&fs5(7 downto 4);addr<="1000"outline<='0'when 16=>data<="00

27、11"&fs5(3 downto 0);addr<="1001"outline<='0'when 17=>data<="0011"&fs6(7 downto 4);addr<="1010"outline<='0'when 18=>data<="0011"&fs6(3 downto 0);addr<="1011"outline<='0'when 19=>

28、;data<="0011"&fs7(7 downto 4);addr<="1100"outline<='0'when 20=>data<="0011"&fs7(3 downto 0);addr<="1101"outline<='0'when 21=>data<="0011"&fs8(7 downto 4);addr<="1110"outline<='

29、;0'when 22=>data<="0011"&fs8(3 downto 0);addr<="1111"outline<='0'when 23=>data<="0011"&tm(7 downto 4);addr<="0101"outline<='1'when 24=>data<="0011"&tm(3 downto 0);addr<="0110"

30、outline<='1'when 25=>data<="0011"&zb(3 downto 0);addr<="1101"outline<='1'when 26=>case teshu is when "01"=> data<="01000110"addr<="1110"outline<='1' -f when "10"=> data<="

31、01000011"addr<="1110"outline<='1' -c when others=> null; end case;when 27=>case teshu is when "01"=> data<="01000111"addr<="1111"outline<='1' -g when "10"=> data<="01010011"addr<="1

32、111"outline<='1' -s when others=> null; end case;when others=> null;end case;end process; end architecture jgt;此模塊采用狀態(tài)機的方法在lcd上按格式顯示搶答器的8個2位bcd碼分數(shù)、搶答的組別、時間。3、主模塊library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the

33、 following library declaration if instantiating- any xilinx primitives in this code.-library unisim;-use unisim.vcomponents.all;entity qdmain1 is port ( teshu : out std_logic_vector (1 downto 0); cpin : in std_logic; keyout : in std_logic_vector (15 downto 0); r : in std_logic; fs1 : out std_logic_v

34、ector (7 downto 0); fs2 : out std_logic_vector (7 downto 0); fs3 : out std_logic_vector (7 downto 0); fs4 : out std_logic_vector (7 downto 0); fs5 : out std_logic_vector (7 downto 0); fs6 : out std_logic_vector (7 downto 0); fs7 : out std_logic_vector (7 downto 0); fs8 : out std_logic_vector (7 down

35、to 0); tm : out std_logic_vector (7 downto 0); zb : out std_logic_vector (3 downto 0);end qdmain1;architecture behavioral of qdmain1 issignal kskey:std_logic:='0'signal yida:std_logic:='0'signal jiaflag,jianflag:std_logic;signal cpct : integer range 0 to 4999;signal cp: std_logic;sig

36、nal cp1s : integer range 0 to 999;signal cpcnt: std_logic; signal tm1 : std_logic_vector (7 downto 0); signal zb1 : std_logic_vector (3 downto 0);- signal f1,f2,f3,f4,f5,f6,f7,f8 : std_logic_vector (7 downto 0); signal fk1,fk2,fk3,fk4,fk5,fk6,fk7,fk8 : std_logic_vector (7 downto 0);begintm<=tm1;z

37、b<=zb1;fs1<=fk1; fs2<=fk2; fs3<=fk3;fs4<=fk4; fs5<=fk5;fs6<=fk6; fs7<=fk7;fs8<=fk8;process(r,cpin)begin if r='1' then cpct<=4999; elsif cpin='1' and cpin 'event then -20mhz if cpct=0 then -cp shi 500us; cpct<=4999;cp<=not cp; else cpct<=cpct

38、-1; end if; end if;end process;process(r,cp)begin if r='1' then cp1s<=0; elsif cp='1' and cp 'event then if cp1s=999 then cp1s<=0; cpcnt<=not cpcnt; -cpcnt shi 1s; else cp1s<=cp1s+1; end if; end if;end process;process(cpin,cpcnt)beginif cpin='1' and cpin '

39、event then if keyout="1000000000000000" then fk1<="00000000" fk2<="00000000" fk3<="00000000"fk4<="00000000" fk5<="00000000" fk6<="00000000"fk7<="00000000" fk8<="00000000" elsif r='1&

40、#39; then yida<='0' kskey<='0' tm1<="00001001" zb1<="0000" teshu<="00" jiaflag<='1' jianflag<='1' else if yida='0' then case keyout is when "0100000000000000"=>kskey<='1' -0 shi kaishi

41、jian when "0000000000000001"=>yida<='1'zb1<="0001" -fk1<=fk1+1; when "0000000000000010"=>yida<='1'zb1<="0010" -fk2<="00000011" when "0000000000000100"=>yida<='1'zb1<="0011"

42、-fk3<="00000011" when "0000000000010000"=>yida<='1'zb1<="0100" -fk4<="00000011" when "0000000000100000"=>yida<='1'zb1<="0101" -fk5<="00000011" when "0000000001000000"=>yida&l

43、t;='1'zb1<="0110" -fk6<="00000011" when "0000000100000000"=>yida<='1'zb1<="0111" -fk7<="00000011" when "0000001000000000"=>yida<='1'zb1<="1000" -fk8<="00000011" -when

44、 "0000001000000000"=>yida<='0'kskey<='0' - 9 qinglingjian when others=>null; end case; if kskey='1' then if cpcnt='1' and cpcnt 'event then if tm1/="00000000" then tm1<=tm1-1; end if; end if; if tm1="00000000" then tesh

45、u<="10" -chao shi end if; end if; else if kskey='0' then teshu<="01" -fan gui if keyout="0010000000000000" then if jianflag='1' then case zb1 is when "0001"=>fk1<=fk1-1; jianflag<='0' when "0010"=>fk2<=fk2

46、-1; jianflag<='0' when "0011"=>fk3<=fk3-1; jianflag<='0' when "0100"=>fk4<=fk4-1; jianflag<='0' when "0101"=>fk5<=fk5-1; jianflag<='0' when "0110"=>fk6<=fk6-1; jianflag<='0' when &q

47、uot;0111"=>fk7<=fk7-1; jianflag<='0' when "1000"=>fk8<=fk8-1; jianflag<='0' when others=>null; end case; end if; end if; else if keyout="0001000000000000" then if jiaflag='1' then case zb1 is when "0001"=>fk1<=fk1+1;jiaflag<='0' when "0010"=>fk2<=fk2+1;jiaflag<='0' when "0011"=>fk3<=fk3+1;jiaflag<='0' when "0100&q

溫馨提示

  • 1. 本站所有資源如無特殊說明,都需要本地電腦安裝OFFICE2007和PDF閱讀器。圖紙軟件為CAD,CAXA,PROE,UG,SolidWorks等.壓縮文件請下載最新的WinRAR軟件解壓。
  • 2. 本站的文檔不包含任何第三方提供的附件圖紙等,如果需要附件,請聯(lián)系上傳者。文件的所有權(quán)益歸上傳用戶所有。
  • 3. 本站RAR壓縮包中若帶圖紙,網(wǎng)頁內(nèi)容里面會有圖紙預覽,若沒有圖紙預覽就沒有圖紙。
  • 4. 未經(jīng)權(quán)益所有人同意不得將文件中的內(nèi)容挪作商業(yè)或盈利用途。
  • 5. 人人文庫網(wǎng)僅提供信息存儲空間,僅對用戶上傳內(nèi)容的表現(xiàn)方式做保護處理,對用戶上傳分享的文檔內(nèi)容本身不做任何修改或編輯,并不能對任何下載內(nèi)容負責。
  • 6. 下載文件中如有侵權(quán)或不適當內(nèi)容,請與我們聯(lián)系,我們立即糾正。
  • 7. 本站不保證下載資源的準確性、安全性和完整性, 同時也不承擔用戶因使用這些下載資源對自己和他人造成任何形式的傷害或損失。

評論

0/150

提交評論