運放基本仿真步驟PPT課件

1、in order to decease the power consumption, ibias is only 30na. to create a symbol of a schematic: from design-create cellview-from cellviewtwo methods of simulating open-loop differential gainis available in ade (analog design environment)in this method, vp=vcm_in +x, and vn=vcm_in-xwhere, vcm_in is

2、 the common voltage, x is a design variables.setup vnsetup vpto add a model for the simulation from ade-setup-model librariesto create a dc sweepfrom ade-analyses-choose-dc_2outcomoutoutcomoutvpnvvvvavvx_0|comoutoutxvvwhere, differential gain is 71.56dbto obtain vcom_out from calculator-special func

3、tions-valuevout -vcom_outto obtain dc gain from calculator-special functions-derivsetup vnsetup vpin this method, vp=vcm_in+ x +vac, and vn=vcm_inwhere, vcm_in is the input common voltage, x is a design variables, vac is a ac voltage for ac sweep.to add a model for the simulation from ade-setup-mode

4、l librariesto create a ac sweepfrom ade-analyses-choose-acfixedfreq1020logvoutavdifferential gain is 65.56db the results of the two methods are different, in fact, method 1 is more accurate for dc gain.11coutccmvcvavavaaacmrr vcaacmrryou can get detail illustration from “cmos analog circuit design”,

5、 phillip e. allen, oxford university press, inc._npcmcominacvvvvvwhere, vcom_in is the input common voltage, vac is a ac voltage for ac sweep.to add a model for the simulation from ade-setup-model librariesto create a ac sweepfrom ade-analyses-choose-ac1/cmrrcmrrto obtain cmrr:from calculator-1/x1/c

6、mrr and cmrr plot directly. to obtain magnitude plot of cmrr: from calculator-db20frequency response of cmrrthe cmrr is 72.14db at low frequency range.to obtain phase plot of cmrr: from calculator-phase1outddvvpsrryou can get detail illustration from “cmos analog circuit design”, phillip e. allen, o

7、xford university press, inc.dddcacvvvwhere, vac is a ac voltage for ac sweep, and vdc is a dc voltage to add a model for the simulation from ade-setup-model librariesto create a ac sweepfrom ade-analyses-choose-ac1/psrrpsrrto obtain cmrr:from calculator-1/x1/psrr and psrr plot directly. to obtain ma

8、gnitude plot of psrr: from calculator-db20frequency response of psrrthe cmrr is 79.17db at low frequency range.to obtain phase plot of psrr: from calculator-phasewhere, vcm_in is the input common voltage, vac is a ac voltage for ac sweep,and cl is the loading capacitor. vcm_invacthe dominant pole is

9、 controlled by cl in folded cascode op amp.to add a model for the simulation from ade-setup-model librariesto create a ac sweepfrom ade-analyses-choose-acto obtain magnitude plot of open-loop: from calculator-db20open-loop frequency responsethe pm is 74o when cl is 5pf.to obtain phase plot of open-l

10、oop: from calculator-phase there have two poles in open-loop frequencyresponse, one is the dominant pole of output net,and the another is the mirror pole caused by active current mirror. where, x is a design variables and cl is the loading capacitor. to add a model for the simulation from ade-setup-

11、model librariesto create a dc sweepfrom ade-analyses-choose-dcicmrthe input common-mode range is 04.2vwhere, vcm_in is the input common voltage, x is a design variables. to obtain osrin this method, vp=vcm_in +x, and vn=vcm_in-xwhere, vcm_in is the common voltage, x is a design variables.setup vnset

12、up vpto add a model for the simulation from ade-setup-model librariesto create a dc sweepfrom ade-analyses-choose-dc you can get the left waveform from page 8.osrthe output swing range is from 842.5mv to 4.381v.ps: osr is dependence of applications and is not constant. where, vcm_in is the input com

13、mon voltage, vac is ac voltage for ac sweep. inininaciicj vvcm_invacto add a model for the simulation from ade-setup-model librariesto create a ac sweepfrom ade-analyses-choose-acthe input capacitor is approximate of 5pfoutoutoutvri the schematic of obtaining open-loop output resistance ro. the equi

14、valent model by using thevenin form on the op amp. 12001200200vooutovarrrrathus, simulating rout and knowing av allows one to calculate the output resistance ro of the op amp.ioutvout200rr=1gvin=0vto add a model for the simulation from ade-setup-model librariesto create a tran sweepfrom ade-analyses

15、-choose-tranioutrout333548585200200outvoramrm the unity-gain configuration places the severest requirements on stabilityand slew rate because its feedback is the largest, resulting in the largest values of loop-gain, and should always be used as a worst-case measurement. the input step magnitude is 2v.to add a model for the simulation from ade-setup-model librariesto create a tranfrom ade-analyses-choose-transr=95.1k v/svcm_invacthe dominant pole is controlled by cl in folde