數(shù)字式競(jìng)賽搶答器VHDL

1、數(shù)字系統(tǒng)設(shè)計(jì)與硬件描述語言期末考試作業(yè)題目： 數(shù)字式競(jìng)賽搶答器設(shè)計(jì) 學(xué)院： 電子信息工程 專業(yè)： 電子信息工程 學(xué)號(hào)： 姓名： 一、 選題設(shè)計(jì)描述1. 功能介紹此設(shè)計(jì)用于競(jìng)賽的四人搶答，有如下的功能：（1） 具有多路搶答功能，臺(tái)數(shù)設(shè)計(jì)為四；（2） 具有搶答器開始后30秒倒計(jì)時(shí)，30秒后無人搶答顯示超時(shí)，并報(bào)警；（3） 能顯示超前搶答犯規(guī)，并警報(bào)；（4） 能顯示各組得分，大隊(duì)加分，答錯(cuò)扣分；當(dāng)系統(tǒng)復(fù)位，主持人按下?lián)尨痖_始按鍵，處于使能狀態(tài)，搶答開始，某路搶答鍵按下時(shí)，該路信號(hào)將其他路信號(hào)鎖存，同時(shí)搶答鈴聲響起，直至此路按鍵松開，顯示該路組號(hào)。2. 算法簡(jiǎn)介本設(shè)計(jì)采用分層設(shè)計(jì)思想，分為：信號(hào)鑒別模

2、塊、計(jì)時(shí)模塊、計(jì)分模塊、BCD譯碼模塊、分頻器，還有頂層模塊。信號(hào)鑒別模塊。此模塊主要實(shí)現(xiàn)搶答器的搶答功能，并能夠分辨是正常搶答還是提前搶答，選取最先按下的一路信號(hào)，鎖存其余信號(hào)，實(shí)現(xiàn)信號(hào)選取功能。在此模塊中，用到的信號(hào)為搶答信號(hào)a、b、c、d;搶答使能信號(hào)en；搶答結(jié)果信號(hào)states；警報(bào)時(shí)鐘信號(hào)clk2；復(fù)位信號(hào)rst；提前搶答信號(hào)fangui。計(jì)時(shí)模塊。此模塊主要實(shí)現(xiàn)搶答過程中的計(jì)時(shí)功能，在搶答開始后進(jìn)行30秒的倒計(jì)時(shí)，且在30秒后顯示無人搶答報(bào)警信號(hào)。其中有搶答時(shí)鐘信號(hào)clk；系統(tǒng)復(fù)位信號(hào)rst；搶答使能信號(hào)en；無人搶答警報(bào)信號(hào)warn；計(jì)時(shí)中止信號(hào)stop；計(jì)時(shí)十位個(gè)位信號(hào)tb，

3、ta。計(jì)分模塊。此模塊主要實(shí)現(xiàn)給四個(gè)搶答器計(jì)分的功能，初始條件下，為每個(gè)搶答器信號(hào)預(yù)制5分，當(dāng)某組搶答且回答正確時(shí)加一分，答錯(cuò)減一分，未獲答題機(jī)會(huì)時(shí)保持不變。其中設(shè)有時(shí)鐘信號(hào)clk；復(fù)位信號(hào)rst；搶答使能信號(hào)en；搶答結(jié)果顯示信號(hào)states；記分加減信號(hào)add（add1時(shí)為加，add0時(shí)為減）；四個(gè)信號(hào)的得分顯示信號(hào)a_out,b_out,c_out,d_out。BCD譯碼模塊。此模塊主要實(shí)現(xiàn)將搶答結(jié)果信號(hào)顯示在bcd七段譯碼器上。其中輸入信號(hào)a；輸出譯碼結(jié)果信號(hào)q。分頻器。此模塊主要實(shí)現(xiàn)時(shí)鐘分頻功能。在開頭對(duì)時(shí)鐘信號(hào)進(jìn)行一次千分頻。其中時(shí)鐘輸入信號(hào)clkin，輸出信號(hào)clk。頂層模塊。將

4、前幾個(gè)模塊綜合在一起，形成一個(gè)整體。分頻器輸出作為其他模塊所需的時(shí)鐘信號(hào)，使整個(gè)系統(tǒng)正常運(yùn)轉(zhuǎn)。二、 程序源代碼及說明搶答信號(hào)鑒別模塊的程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity qdjb is port(clk2,en,rst:in std_logic; a,b,c,d:in std_logic; fangui:out std_logic; states:out std_logic_vector(3 downto 0);end qdjb;architecture one o

5、f qdjb issignal sinor,fanguif,tmp:std_logic;signal cnt:std_logic_vector(5 downto 0);beginsinor<=a or b or c or d;p1:process(a,rst,b,c,d,tmp) begin if rst='1' then -復(fù)位信號(hào)有效，系統(tǒng)復(fù)位。 tmp<='1'states<="0000" elsif tmp='1' then if a='1' then -判斷哪路信號(hào)變化，進(jìn)行選取 s

6、tates<="0001"tmp<='0' -對(duì)states進(jìn)行置數(shù) elsif b='1' then states<="0010"tmp<='0' elsif c='1' then states<="0011"tmp<='0' elsif d='1' then states<="0100"tmp<='0' else tmp<='1's

7、tates<="0000" end if ; end if;end process p1; p2:process(clk2,en,rst,cnt) -判斷是否提前搶答并報(bào)警 begin if rst='1' then cnt<="000000"fanguif<='0' -初始化提前搶答犯規(guī)信號(hào) elsif clk2'event and clk2='1' then if en='0' and sinor='1' then if cnt<"

8、;111111" then fanguif<=not fanguif;cnt<=cnt+1; else fanguif<='0' end if; end if; end if;end process p2;fangui<=fanguif;end one;計(jì)時(shí)模塊的程序：library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity js is port(clk,rst,en,stop:in std_logic; warn:buffer std_lo

9、gic; ta,tb:buffer std_logic_vector(3 downto 0);end js;architecture one of js issignal co:std_logic;beginp1:process(clk,rst,en,stop,ta) -個(gè)位計(jì)時(shí)信號(hào)進(jìn)行0到9循環(huán)計(jì)數(shù) begin if rst='1' or stop='1' then ta<="0000" elsif clk'event and clk='1' then co<='0' if en='

10、;1' then if ta="0000" then ta<="1001"co<='1' else ta<=ta-1; end if; end if; end if;end process p1;p2:process(co,rst,en,stop,tb) -十位計(jì)時(shí)信號(hào)0到3變化 begin if rst='1' or stop='1' then tb<="0011" elsif co'event and co='1' then i

11、f en='1' then if tb="0000" then tb<="0011" else tb<=tb-1; end if; end if; end if;end process p2;p3:process(rst,ta,tb) -計(jì)時(shí)時(shí)間到達(dá)，報(bào)警 begin if rst='1' then warn<='0' elsif ta="0000" and tb="0000" then warn<='1' else warn&

12、lt;='0' end if;end process p3;end one;計(jì)分模塊的程序：library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jf is port(clk,rst,en,add:in std_logic; states:in std_logic_vector(3 downto 0); a_out,b_out,c_out,d_out:buffer std_logic_vector(3 downto 0);end jf;architecture one o

13、f jf is beginp1:process(clk,rst,add,states,a_out,b_out,c_out,d_out) begin if (rst='1') then a_out<="0101"b_out<="0101"c_out<="0101"d_out<="0101" -初始化置5分 elsif en='1'then if clk'event and clk='1' then case states is when

14、"0001"=> if add='1' then -add信號(hào)為高時(shí)，加1分 if a_out="1111" then -最多15分 a_out<="0000" else a_out<=a_out+1; end if; elsif add='0' then -add信號(hào)為0，減1分 if a_out="0000" then a_out<="0000" else a_out<=a_out-1; end if; end if; when

15、"0010"=> if add='1' then if b_out="1111" then b_out<="0000" else b_out<=b_out+1; end if; elsif add='0' then if b_out="0000" then b_out<="0000" else b_out<=b_out-1; end if; end if; when "0011"=> if add='

16、1' then if c_out="1111" then c_out<="0000" else c_out<=c_out+1; end if; elsif add='0' then if c_out="0000" then c_out<="0000" else c_out<=c_out-1; end if; end if; when "0100"=> if add='1' then if d_out="1111&qu

17、ot; then d_out<="0000" else d_out<=d_out+1; end if; elsif add='0' then if d_out="0000" then d_out<="0000" else d_out<=d_out-1; end if; end if; when others=> a_out<=a_out;b_out<=b_out;c_out<=c_out;d_out<=d_out; end case; end if;end if;e

18、nd process p1;end one;搶答器頂層模塊程序：library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity qiangda is port(clkin,clk2,en,a,b,c,d,add,stop,rst:in std_logic; fangui,alarm:out std_logic; ta,tb:buffer std_logic_vector(3 downto 0); states:buffer std_logic_vector(3 downto 0); stateso

19、ut:out std_logic_vector(0 to 6); a_out,b_out,c_out,d_out:buffer std_logic_vector(3 downto 0);end qiangda;architecture bhv of qiangda iscomponent qdjb is port(clk2,en,rst:in std_logic; a,b,c,d:in std_logic; fangui:out std_logic; states:out std_logic_vector(3 downto 0);end component;component js is po

20、rt(clk,rst,en,stop:in std_logic; warn:buffer std_logic; ta,tb:buffer std_logic_vector(3 downto 0);end component;component jf is port(clk,rst,en,add:in std_logic; states:in std_logic_vector(3 downto 0); a_out,b_out,c_out,d_out:buffer std_logic_vector(3 downto 0);end component;component BCD7 isport(a:

21、in std_logic_vector(3 downto 0);q:out std_logic_vector(0 to 6);end component BCD7;component divf is port(clk: IN STD_LOGIC; q : OUT STD_LOGIC; qn: OUT std_logic_vector(9 downto 0);end component divf;signal cnt:std_logic_vector(3 downto 0);signal clk: STD_LOGIC;signal divqn: std_logic_vector(3 downto

22、 0);beginu1:qdjb port map(clk2,en,rst,a,b,c,d,fangui,states);u2:js port map(clk,rst,en,stop,alarm,ta,tb);u3:jf port map(clk,rst,en,add,states,a_out,b_out,c_out,d_out);u4:BCD7 port map(states,statesout);u5:divf port map(clkin,clk,divqn);end bhv;BCD7段譯碼器模塊程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;EN

23、TITY BCD7 ISPORT(a: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -數(shù)據(jù)輸入 q : OUT STD_LOGIC_VECTOR(0 TO 6) ); -7段輸出END BCD7;ARCHITECTURE behav OF BCD7 IS BEGIN PROCESS (a) BEGIN case a(3 downto 0) is - BCD 7段譯碼表 when "0000" => q<="1111110" when "0001" => q<="0110000&q

24、uot; when "0010" => q<="1101101"when "0011" => q<="1111001" when "0100" => q<="0110011" when "0101" => q<="1011011" when "0110" => q<="1011111"when "0111" =>

25、 q<="1110000" when "1000" => q<="1111111"when "1001" => q<="1111011" when others => q<="0000000" END case; END PROCESS; END behav;一千分頻器模塊程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_unsigned.ALL;ENTITY

26、 divf ISPORT(clk: IN STD_LOGIC; q : OUT STD_LOGIC; qn: OUT std_logic_vector(9 downto 0);END divf;ARCHITECTURE behav OF divf IS signal rst: std_logic; signal qn1:std_logic_vector(9 downto 0); BEGIN PROCESS (clk,rst) BEGIN if rst='1' then qn1<= "0000000000" elsif clk'event and

27、 clk='1' then qn1<=qn1+1; end if; END PROCESS; rst<='1' when qn1=1000 else '0' qn<=qn1; -計(jì)數(shù) q<=qn1(9); -分頻輸出,1000分頻END behav;三、 仿真結(jié)果及分析系統(tǒng)總體框圖：對(duì)于各個(gè)模塊的仿真測(cè)試所得結(jié)果，仿真波形分析如下：1、 信號(hào)鑒別模塊：仿真結(jié)果： 本模塊主要實(shí)現(xiàn)搶答功能。當(dāng)rst信號(hào)為1，en信號(hào)為1時(shí)，搶答開始，當(dāng)有一路正常獲得搶答時(shí)，系統(tǒng)會(huì)自動(dòng)封鎖另外三路的搶答信號(hào)，只允許一人處于答題狀態(tài)；當(dāng)主持人沒有

28、允許搶答時(shí)，若有人超前搶答，警報(bào)會(huì)響起，同時(shí)只要有人搶答那么搶答顯示臺(tái)（states）會(huì)顯示哪一個(gè)在搶答。如上圖示，在系統(tǒng)第一個(gè)復(fù)位信號(hào)來臨后，電路自動(dòng)復(fù)位，在允許搶答信號(hào)來臨之前（即en=0），b臺(tái)超前搶答，此時(shí)警報(bào)響起（即超前搶答警報(bào)信號(hào)fangui獲得一個(gè)頻率很高的脈沖，就會(huì)響起），之后主持人復(fù)位，并允許搶答，a臺(tái)最先搶答，此時(shí)搶答顯示臺(tái)顯示其臺(tái)號(hào)1。2、 計(jì)時(shí)模塊：仿真結(jié)果：本模塊主要實(shí)現(xiàn)計(jì)時(shí)功能。當(dāng)rst信號(hào)為1時(shí)，計(jì)時(shí)復(fù)位為30秒倒計(jì)時(shí)，主持人允許的en信號(hào)為1時(shí)，開始進(jìn)行倒計(jì)時(shí)，系統(tǒng)時(shí)鐘每來一個(gè)上升沿，倒計(jì)時(shí)減1，當(dāng)?shù)?0秒倒計(jì)時(shí)計(jì)玩仍然無人搶答時(shí)，警報(bào)指示燈亮(即warn=1)，若有人搶答主持人可以按下中止鍵（即stop=1），這樣倒計(jì)時(shí)就會(huì)回到30秒初始狀態(tài)。圖示的情況為在倒計(jì)時(shí)16秒時(shí)，主持人按下中止鍵，計(jì)時(shí)器變