湖南工業(yè)大學(xué)秒表eda實驗報告

1、EDA實驗報告學(xué)院：電氣學(xué)院班級：學(xué)號姓名：實驗六 數(shù)字秒表的設(shè)計1. 實驗?zāi)康模?） 進一步熟悉掌握Quartus 。（2） 進一步熟悉和掌握GW48-CK或其他EDA實驗開發(fā)系統(tǒng)的應(yīng)用。（3） 學(xué)習(xí)和掌握VHDL進程語句和元件例化語句的使用。2. 實驗內(nèi)容設(shè)計并調(diào)試好數(shù)字秒表,并用GW48-CK或其他EDA實驗開發(fā)系統(tǒng)進行硬件驗證。3. 實驗條件（1） 開發(fā)軟件：Quartus 。（2） 實驗設(shè)備：GW48-CK EDA實驗開發(fā)系統(tǒng)。（3） 擬用芯片：EP3C55F484C8.4. 實驗設(shè)計1） 系統(tǒng)原理框圖本實驗是由3MHZ100HZ分頻器、六進制計數(shù)器、十進制計數(shù)器、動態(tài)顯示控制器CL

2、KGEN、數(shù)據(jù)動態(tài)顯示控制DISPLAY和數(shù)字秒表組成。 數(shù)字秒表電路邏輯圖2） VHDL程序-3MHZ100HZ分頻器CTRLS.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CTRLS IS PORT(CLK: IN STD_LOGIC; SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);END ENTITY CTRLS;ARCHITECTURE ART OF CTRLS IS SIGNAL CNT: STD_LOGIC_VECTOR(2 DOW

3、NTO 0); BEGIN PROCESS(CLK) IS BEGIN IF CLK'EVENT AND CLK='1' THEN IF CNT="111" THEN CNT<="000" ELSE CNT<=CNT+'1' END IF ; END IF; END PROCESS; SEL<=CNT;END ARCHITECTURE ART;六進制計數(shù)器CNT6LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED

4、.ALL;ENTITY CNT6 IS PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; ENA:IN STD_LOGIC; CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC);END ENTITY CNT6;ARCHITECTURE ART OF CNT6 IS SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,CLR,ENA) IS BEGIN IF CLR='1' THEN CQI<="0000&qu

5、ot; ELSIF CLK'EVENT AND CLK='1' THEN IF ENA='1' THEN IF CQI="0101" THEN CQI<="0000" ELSE CQI<=CQI+'1' END IF; END IF; END IF; END PROCESS; PROCESS(CQI) IS BEGIN IF CQI="0000" THEN CO<='1' ELSE CO<='0' END IF; END P

6、ROCESS; CQ<=CQI;END ARCHITECTURE ART;十進制計數(shù)器CNT10LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 IS PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; ENA:IN STD_LOGIC; CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC);END ENTITY CNT10;ARCHITECTURE ART OF CNT10 IS

7、SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,CLR,ENA) IS BEGIN IF CLR='1' THEN CQI<="0000" ELSIF CLK'EVENT AND CLK='1' THEN IF ENA='1' THEN IF CQI="1001" THEN CQI<="0000" ELSE CQI<=CQI+'1' END IF; END IF; END IF

8、; END PROCESS; PROCESS(CLK,CQI) IS BEGIN IF CLK'EVENT AND CLK='1' THEN IF CQI<"1001" THEN CO<='0' ELSE CO<='1' END IF; END IF; END PROCESS; CQ<=CQI;END ARCHITECTURE ART;動態(tài)顯示控制器CLKGENLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CLKGEN IS PORT (CLK:

9、IN STD_LOGIC; NEWCLK:OUT STD_LOGIC);END ENTITY CLKGEN;ARCHITECTURE ART OF CLKGEN IS SIGNAL CNT:INTEGER RANGE 0 TO 10#29999#; BEGIN PROCESS(CLK) IS BEGIN IF CLK'EVENT AND CLK='1' THEN IF CNT=10#29999# THEN CNT<=0; ELSE CNT<=CNT+1; END IF; END IF; END PROCESS; PROCESS(CNT) IS BEGIN I

10、F CNT=10#29999# THEN NEWCLK<='1' ELSE NEWCLK<='0' END IF; END PROCESS;END ARCHITECTURE ART;數(shù)據(jù)動態(tài)顯示控制器DISPLAYLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DISPLAY IS PORT(SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DATAIN: IN STD_LOGIC_VECTOR(23 DOWNTO

11、 0); COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY DISPLAY;ARCHITECTURE ART OF DISPLAY IS SIGNAL DATA:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(SEL) IS BEGIN CASE SEL IS WHEN "000" => COM<="11111110" WHEN "001" => COM

12、<="11111101" WHEN "010" => COM<="11111011" WHEN "011" => COM<="11110111" WHEN "100" => COM<="11101111" WHEN "101" => COM<="11011111" WHEN "110" => COM<="10111111&

13、quot; WHEN "111" => COM<="01111111" WHEN OTHERS => COM<="11111111" END CASE ; END PROCESS; PROCESS(SEL) IS BEGIN CASE SEL IS WHEN "000" =>DATA<=DATAIN(3 DOWNTO 0); WHEN "001" =>DATA<=DATAIN(7 DOWNTO 4); WHEN "010" =&

14、gt;DATA<=DATAIN(11 DOWNTO 8); WHEN "011" =>DATA<=DATAIN(15 DOWNTO 12);WHEN "100" =>DATA<=DATAIN(19 DOWNTO 16);WHEN "101" =>DATA<=DATAIN(23 DOWNTO 20); WHEN OTHERS=>DATA<="0000" END CASE; CASE DATA IS WHEN "0000" => SEG&l

15、t;="00111111"-3FH WHEN "0001" => SEG<="00000110"-06H WHEN "0010" => SEG<="01011011"-5BH WHEN "0011" => SEG<="01001111"-4FH WHEN "0100" => SEG<="01100110"-66H WHEN "0101" =>

16、SEG<="01101101"-6DH WHEN "0110" => SEG<="01111101"-7DH WHEN "0111" => SEG<="00000111"-07H WHEN "1000" => SEG<="01111111"-7FH WHEN "1001" => SEG<="01101111"-6FH WHEN OTHERS => SEG&l

17、t;="00000000"-00H END CASE ; END PROCESS;END ARCHITECTURE ART;數(shù)字秒表TIMES -TIMES.VHDLLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TIMES ISPORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; ENA:IN STD_LOGIC; CLK2:IN STD_LOGIC; COM:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0

18、);DOUT1: OUT STD_LOGIC_VECTOR(23 DOWNTO 0); END ENTITY TIMES;ARCHITECTURE ART OF TIMES ISCOMPONENT CLKGEN ISPORT(CLK:IN STD_LOGIC; NEWCLK:OUT STD_LOGIC);END COMPONENT CLKGEN;COMPONENT CNT10 ISPORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; ENA:IN STD_LOGIC; CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_L

19、OGIC);END COMPONENT CNT10;COMPONENT CNT6 ISPORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; ENA:IN STD_LOGIC; CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC);END COMPONENT CNT6;COMPONENT CTRLS ISPORT(CLK:IN STD_LOGIC; SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);END COMPONENT CTRLS;COMPONENT DISPLAY ISPORT(S

20、EL:IN STD_LOGIC_VECTOR(2 DOWNTO 0); DATAIN:IN STD_LOGIC_VECTOR(23 DOWNTO 0); COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT DISPLAY;SIGNAL S0:STD_LOGIC;SIGNAL S1,S2,S3,S4,S5:STD_LOGIC;SIGNAL S:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL DOUT:STD_LOGIC_VECTOR(23 DOWNTO 0);BEGINU0:CLKGEN PORT MAP(CLK=>CLK,NEWCLK=>S0);U1:C