江蘇大學(xué)數(shù)字邏輯課程設(shè)計(jì)數(shù)字時(shí)鐘(共12頁)

1、精選優(yōu)質(zhì)文檔-傾情為你奉上JIANGSU NIVERSITY課程設(shè)計(jì)報(bào)告學(xué)院：計(jì)算機(jī)科學(xué)與通信工程班級(jí)：網(wǎng)絡(luò)工程姓名：學(xué)號(hào)：指導(dǎo)老師：報(bào)告日期 ：2016年1月15日專心-專注-專業(yè)目 錄.設(shè)計(jì)目的 設(shè)計(jì)一個(gè)擁有：正常的時(shí)分秒計(jì)數(shù)功能，實(shí)現(xiàn)校時(shí)校分清零的功能，利用揚(yáng)聲器實(shí)現(xiàn)整點(diǎn)報(bào)時(shí)和鬧鐘功能的多功能數(shù)字鐘。.設(shè)計(jì)內(nèi)容 整個(gè)系統(tǒng)分成七個(gè)模塊進(jìn)行：計(jì)時(shí)模塊、校時(shí)模塊、整點(diǎn)報(bào)時(shí)模塊、分頻模塊、動(dòng)態(tài)掃描模塊，動(dòng)態(tài)顯示模塊、鬧鐘模塊。l、能進(jìn)行正常的時(shí)、分、秒計(jì)時(shí)功能，分別由6個(gè)數(shù)碼顯示24小時(shí)、60分鐘的計(jì)數(shù)器顯示。2、能利用實(shí)驗(yàn)系統(tǒng)上的按鈕實(shí)現(xiàn)“校時(shí)”、“校分”功能；3、能利用揚(yáng)聲器做整點(diǎn)

2、報(bào)時(shí)：4、定時(shí)鬧鐘功能5、用層次化設(shè)計(jì)方法設(shè)計(jì)該電路，用硬件描述語言編寫各個(gè)功能模塊。6、報(bào)時(shí)功能。報(bào)時(shí)功能用功能仿真的仿真驗(yàn)證，可通過觀察有關(guān)波形確認(rèn)電路設(shè)計(jì)是否正確。.設(shè)計(jì)原理1 計(jì)時(shí)模塊：使用一個(gè)二十四進(jìn)制和兩個(gè)六十進(jìn)制計(jì)數(shù)器級(jí)聯(lián)，構(gòu)成數(shù)字鐘的基本框架。二十四進(jìn)制用于計(jì)時(shí)，六十進(jìn)制用于計(jì)分和計(jì)秒。給秒計(jì)數(shù)器一個(gè)1hz的時(shí)鐘脈沖，分計(jì)數(shù)器以秒計(jì)數(shù)器的進(jìn)位作為計(jì)數(shù)脈沖，時(shí)計(jì)數(shù)器以分計(jì)數(shù)器的進(jìn)位作為計(jì)數(shù)脈沖。2 校時(shí)模塊：分別按下校時(shí)鍵和校分鍵，計(jì)數(shù)器增至所需時(shí)分?jǐn)?shù)，按下清零鍵，秒計(jì)數(shù)器歸零。此處注意事項(xiàng)：按鍵“抖動(dòng)”消除。利用觸發(fā)器，如D觸發(fā)器，利用D觸發(fā)器邊沿觸發(fā)的特性，在除去時(shí)鐘邊沿來之

3、前一瞬間之外的絕大部分時(shí)間都不能接受輸入，從而實(shí)現(xiàn)“消抖”。校分時(shí)，分計(jì)數(shù)器計(jì)數(shù)不應(yīng)對(duì)小時(shí)位產(chǎn)生影響，因而需要屏蔽此時(shí)分計(jì)數(shù)器的進(jìn)位信號(hào)。需要設(shè)計(jì)二路選擇器對(duì)于正常計(jì)數(shù)以及校時(shí)進(jìn)行選擇。3 整點(diǎn)報(bào)時(shí)模塊：計(jì)時(shí)到59分50秒，每?jī)擅胍淮蔚鸵魣?bào)時(shí)，整點(diǎn)進(jìn)行高音報(bào)時(shí)，將報(bào)時(shí)信號(hào)接到實(shí)驗(yàn)板上的揚(yáng)聲器輸出。、4 分頻模塊：通過不同進(jìn)制的計(jì)數(shù)將1khz的時(shí)鐘脈沖分頻出不同頻率的時(shí)鐘脈沖，以實(shí)現(xiàn)系統(tǒng)對(duì)多頻率時(shí)鐘信號(hào)的需求。5動(dòng)態(tài)顯示模塊：利用6個(gè)數(shù)碼管，將時(shí)分秒按照高低位輸出到數(shù)碼管上。其中掃描頻率超過人眼視覺暫留頻率就可以實(shí)現(xiàn)六個(gè)管同時(shí)顯示的視覺效果。6 鬧鐘模塊：需要新的計(jì)數(shù)器進(jìn)行定時(shí)鬧鐘信號(hào)的存儲(chǔ)，與

4、正常計(jì)時(shí)狀態(tài)實(shí)現(xiàn)切換，設(shè)計(jì)一個(gè)比較模塊使鬧鐘和計(jì)時(shí)相等時(shí)，開始鳴叫，同時(shí)需要一個(gè)按鍵能夠控制鬧鐘的開關(guān)。.具體實(shí)現(xiàn)（1）頂層圖圖一：頂層圖（2）代碼1.24進(jìn)制：時(shí)計(jì)數(shù)器：模塊圖如圖。24進(jìn)制無進(jìn)位計(jì)數(shù)器，當(dāng)計(jì)數(shù)信號(hào)計(jì)到23后再檢測(cè)到計(jì)數(shù)信號(hào)時(shí)會(huì)自動(dòng)歸零。帶清零，clk輸入為分秒進(jìn)位相與的結(jié)果。qh為十位，ql為個(gè)位。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt24 isport(clk:in std_logic; qh,ql:out std_logic_vector(3

5、downto 0); tc:out std_logic);end cnt24;architecture one of cnt24 is begin process(clk) variable iql,iqh:std_logic_vector(3 downto 0):="0000" begin if clk'event and clk='1' then iql:=iql+1; if iql="1010" then iqh:=iqh+1; iql:="0000" end if; if (iqh="0010

6、")and(iql="0100") then iqh:="0000" iql:="0000" end if; end if; ql<=iql; qh<=iqh; end process; end one; 2. 60進(jìn)制： 秒計(jì)數(shù)器模塊設(shè)計(jì)：六十進(jìn)制帶進(jìn)位計(jì)數(shù)器，可清零，clk輸入信號(hào)為1Hz脈沖，當(dāng)ql計(jì)滿9后qh增加1，當(dāng)ql滿9且qh記滿5，ql、qh同時(shí)歸零，co輸出為高電平。qh為十位ql為個(gè)位。library ieee;use ieee.std_logic_1164.all;use ieee.std_

7、logic_unsigned.all;entity cnt60 is port(clk,clr:in std_logic; ql,qh:buffer std_logic_vector(3 downto 0); tc:out std_logic );end cnt60;architecture behavor of cnt60 isbegin tc<='0' when(clk='1' and ql="0000" and qh="0110") else '1' process(clk,clr,ql,qh)

8、variable iql,iqh:std_logic_vector(3 downto 0); begin if(clr='0'or (iql="0000" and iqh="0110")then iql:="0000" iqh:="0000" else if(clk'event and clk='1')then iql:=iql+1; if(iql="1010")then iql:="0000" iqh:=qh+1; end if; e

9、nd if;end if;ql<=iql;qh<=iqh;end process;END behavor;分計(jì)數(shù)器同上。注：不同之處為分的clk輸入信號(hào)為秒的進(jìn)位信號(hào)。3.動(dòng)態(tài)顯示：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY dtsm is port( clk:in std_logic; h:in std_logic_vector(7 downto 0); m:in std_logic_vector(7 downto 0); s:in std_logic_vecto

10、r(7 downto 0); seg7out:out std_logic_vector(6 downto 0); sel:buffer std_logic_vector(2 downto 0) );END dtsm;ARCHITECTURE beha of dtsm is signal key:std_logic_vector(3 downto 0); BEGIN PROCESS(clk) variable dount:std_logic_vector(2 downto 0):="000" BEGIN IF(rising_edge(clk)then IF dount=&qu

11、ot;111" then dount:="000" ELSE dount:=dount+1; END IF; END IF; sel<=dount; end process; PROCESS(sel) BEGIN CASE sel IS when "000"=>key<=h(7 downto 4); when "001"=>key<=h(3 downto 0); when "010"=>key<="1010" when "011&qu

12、ot;=>key<=m(7 downto 4); when "100"=>key<=m(3 downto 0); when "101"=>key<="1010" when "110"=>key<=s(7 downto 4); when "111"=>key<=s(3 downto 0); when others=>null; END CASE; END PROCESS; PROCESS (key) BEGIN case key i

13、s when"0000"=>seg7out<="" when"0001"=>seg7out<="" when"0010"=>seg7out<="" when"0011"=>seg7out<="" when"0100"=>seg7out<="" when"0101"=>seg7out<=""

14、; when"0110"=>seg7out<="" when"0111"=>seg7out<="" when"1000"=>seg7out<="" when"1001"=>seg7out<="" when"1010"=>seg7out<="" when others=>null; END CASE; END PROCESS; END

15、 beha;4. 分頻器：模塊圖如圖。由四個(gè)分頻器構(gòu)成，輸入信號(hào)in_clk為1024Hz脈沖信號(hào)。把輸入的1024Hz信號(hào)分頻為四個(gè)脈沖信號(hào)，即1Hz的秒脈沖，4Hz的校時(shí)、校分脈沖，64Hz的消抖脈沖，以及512Hz的蜂鳴器低音輸入。：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY freq_divider IS PORT(clk : IN STD_LOGIC; hz1 : OUT STD_LOGIC; hz4 : OUT

16、 STD_LOGIC; hz64 : OUT STD_LOGIC; hz512 : OUT STD_LOGIC);END freq_divider;ARCHITECTURE rtl OF freq_divider IS SIGNAL count : STD_LOGIC_VECTOR(9 DOWNTO 0);BEGIN PROCESS(clk) BEGIN IF (clk'event and clk='1') THEN IF(count="") THEN Count <= (OTHERS =>'0'); ELSE Count

17、 <= count +1; END IF ; END IF ; END PROCESS; hz512 <= count(0); hz64 <= count(3); hz4 <= count(7); hz1 <= count(9);END rtl;5. 二路選擇器：模塊圖如圖。用以進(jìn)行正常計(jì)時(shí)和校時(shí)/分的選擇。alarm為經(jīng)過消抖的校時(shí)/分信號(hào)。當(dāng)按鍵未曾按下時(shí)，即校時(shí)/分信號(hào)沒有到來時(shí)，二選一選擇器會(huì)選擇輸出a（正常計(jì)時(shí)輸入）信號(hào)，否則當(dāng)alarm按鍵按下時(shí)輸出y為校時(shí)/分輸入信號(hào)4Hz。library ieee;use ieee.std_logic_1164.a

18、ll;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sel2 isport(sel:in std_logic; ip: in std_logic; a,b:out std_logic);end sel2;architecture beh of sel2 isbegin process(sel) begin if(sel='0')then a<=ip; else b<=ip; end if; end process;end beh;6.整點(diǎn)報(bào)時(shí)：整點(diǎn)報(bào)時(shí)及鬧時(shí)：模塊圖如圖在59分

19、52秒、54秒、56秒、58秒給揚(yáng)聲器賦以低音512Hz信號(hào),在00分00秒給揚(yáng)聲器賦以高音1024Hz信號(hào),當(dāng)系統(tǒng)時(shí)間與鬧鈴時(shí)間相同時(shí)給揚(yáng)聲器賦以高音1024Hz信號(hào)。鬧時(shí)時(shí)間為一分鐘。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity zdbs isport(mh,ml,sh,sl:in std_logic_vector(3 downto 0); sig500,sig1k: out std_logic);end zdbs;architecture behavior of zdbs i

20、sbegin sig500<='1' when mh="0101"and ml="1001"and sh="0101"and( sl="0000"or sl="0010" or sl="0100"or sl="0110"or sl="1000") else '0'sig1k<='1' when mh="0000"and ml="0000"

21、and sh="0000"and sl="0000" else '0'end behavior;7.鬧鐘設(shè)置：鬧鐘時(shí)間的設(shè)定：模塊圖如圖。由開關(guān)K1選擇鬧鐘和時(shí)間。由S1、S2脈沖鍵調(diào)節(jié)時(shí)、分。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity alarmset isport(sel:in std_logic; hclo,mclo,sclo,halr,malr,salr: i

22、n std_logic_vector(7 downto 0); h,s,m:out std_logic_vector(7 downto 0);end alarmset;architecture beh of alarmset isbegin process(sel) begin if(sel='0')then h<=hclo; m<=mclo; s<=sclo; else h<=halr; m<=malr; s<="" end if; end process;end beh;8.alarmcmp:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity alarmcmp isport( h,m,halr,malr: in std_logic_vector(7 downto 0); stop:in std_logic; sig:out std_logic); e