ADI ADP2325雙路5A 20V同步降壓電源解決方案

1、adi adp2325雙路5a 20v同步降壓電源解決方案公司的adp2325是雙路5a 20v同步降壓dc/dc穩(wěn)壓器,集成了兩個高邊功率和兩個用來驅(qū)動外接n溝mosfet的低邊驅(qū)動器.兩個通路可配置成兩路5a或10a輸出,輸入4.5v到20v,輸出電壓低至0.6v,主要用在通信設(shè)備,網(wǎng)絡(luò)和服務(wù)器,工業(yè)和儀表,醫(yī)療保健等.本文介紹了adp2325主要特性,功能方框圖,多種典型應(yīng)用,以及評估板adp2325-evalz主要特性,材料清單和元件布局圖.the adp2325 is a full featured, dual output, step-down dc-to-dc regulator

2、 based on a current mode architecture. the adp2325 integrates two high-side power mosfets and two low-side drivers for the external n-channel mosfets. the two pulse-width mod-ulation (pwm) channels can be configured to deliver dual 5 a outputs or a parallel-to-single 10 a output. the regulator opera

3、tes from input voltages of 4.5 v to 20 v, and the output voltage can be as low as 0.6 v.the switching frequency can be programmed from 250 khz to 1.2 mhz, or it can be synchronized to an external clock to minimize interference in multirail applications. the dual pwm channels run 180° out of pha

4、se, thereby reducing input current ripple as well as reducing the size of the input capacitor.the bidirectional synchronization pin can be programmed at a 60°, 90°, or 120° phase shift to provide for a stackable, multi-phase power solution.the adp2325 can be configured to operate in p

5、ulse frequency modulation (pfm) mode at a light load for higher efficiency or in forced pwm mode for noise sensitive applications. external compensation and soft start provide design flexibility.independent enable inputs and power-good outputs provide reliable power sequencing. to enhance system rel

6、iability, the device includes undervoltage lockout (uvlo), overvoltage protection (ovp), overcurrent protection, and thermal shutdown.the adp2325 operates over the 40 to +125 junction temperature range and is available in a 32-lead lfcsp_wq package.adp2325主要特性:input voltage: 4.5 v to 20 v±1% ou

7、tput accuracyintegrated 48 m typical high-side mosfetflexible output configurationdual output: 5 a/5 aparallel single output: 10 aprogrammable switching frequency: 250 khz to 1.2 mhzexternal synchronization input with programmable phase shift or internal clock outputselectable pwm or pfm mode operationadjustable current limit for small inductorsexternal compensation and soft startstartup into precharged outputsupported by adisimpowertm design tooladp2325應(yīng)用:communications infrastructur