參考答案上機(jī)練習(xí)二：組合邏輯電路設(shè)計(jì)

1、VHDL與復(fù)雜數(shù)字系統(tǒng)設(shè)計(jì)上機(jī)實(shí)驗(yàn)2：組合邏輯電路的VHDL程序設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康模?. 掌握在MaxplusII中，使用硬件描述語(yǔ)言設(shè)計(jì)電路的基本操作步驟；2. 運(yùn)用所學(xué)VHDL的描述語(yǔ)句完成組合邏輯電路的設(shè)計(jì)。二、 實(shí)驗(yàn)任務(wù)：從下列各題中任選一題完成。1. 試用兩種描述方法，設(shè)計(jì)一個(gè)四位乘法運(yùn)算器，并對(duì)兩種方法所描述電路的性能進(jìn)行比較。該乘法器有兩個(gè)操作數(shù)輸入端口，有一個(gè)乘積結(jié)果輸出端口，采用標(biāo)準(zhǔn)邏輯位或位矢量數(shù)據(jù)類型。2. 試用兩種描述方法，設(shè)計(jì)一個(gè)四位全減器，并對(duì)兩種方法所描述電路的性能進(jìn)行比較。該減法器有兩個(gè)操作數(shù)輸入端口、一個(gè)借位輸入端口、一個(gè)結(jié)果輸出端口、一個(gè)借位輸出端口，采用標(biāo)

2、準(zhǔn)邏輯位或位矢量數(shù)據(jù)類型。3. 設(shè)計(jì)一個(gè)四位十進(jìn)制數(shù)顯示器，每一個(gè)字碼都由一個(gè)BCD碼7段譯碼顯示器驅(qū)動(dòng)，即該電路包括4個(gè)BCD碼7段譯碼顯示器，要求該電路必須設(shè)計(jì)成能夠自動(dòng)去掉4位中高位上的零，比如十進(jìn)制數(shù)0908，顯示時(shí)應(yīng)為908，故BCD碼7段譯碼顯示器應(yīng)具有滅零功能。該電路的端口包括：四個(gè)BCD碼輸入端口、四個(gè)7段譯碼輸出端口。三、 實(shí)驗(yàn)報(bào)告要求：給出完整的VHDL語(yǔ)言程序，程序應(yīng)包括：庫(kù)和包集合說(shuō)明（必要時(shí)）、實(shí)體和結(jié)構(gòu)體；若使用了元件，要給出底層元件的VHDL語(yǔ)言描述；給出系統(tǒng)自動(dòng)生成的引腳框圖；對(duì)所設(shè)計(jì)電路進(jìn)行功能仿真；進(jìn)行適當(dāng)分析。四、 參考答案：1. 乘法器方法一 利用算術(shù)運(yùn)

3、算符、包集合定義library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mula isport( a,b :in std_logic_vector(3 downto 0); c :out std_logic_vector(7 downto 0);end mula;architecture rtl of mula isbegin c<=a*b;end rtl;* DEVICE SUMMARY *Chip/ Input Output Bidir LCsPOF Device Pins Pin

4、s Pins LCs % Utilizedmula EPF6010ATC100-1 8 8 0 32 3 %User Pins: 8 8 0 方法二 利用部分積連加法library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mulb isport( a,b :in std_logic_vector(3 downto 0); c :out std_logic_vector(7 downto 0);end mulb;architecture rtl of mulb issignal tmp1:st

5、d_logic_vector(3 downto 0);signal tmp2:std_logic_vector(4 downto 0);signal tmp3:std_logic_vector(5 downto 0);signal tmp4:std_logic_vector(6 downto 0);begin tmp1<= a when b(0)='1' else "0000" tmp2<= a & '0' when b(1)='1' else "00000" tmp3<= a &

6、amp; "00" when b(2)='1' else "000000" tmp4<= a & "000" when b(3)='1' else "0000000" c<=tmp1 +tmp2 +tmp3 +('0' & tmp4);end rtl;* DEVICE SUMMARY *Chip/ Input Output Bidir LCsPOF Device Pins Pins Pins LCs % Utilizedmulb EPF60

7、10ATC100-1 8 8 0 29 3 %User Pins: 8 8 0 減法器輸入減法器輸出abc0subc100000001110101101101100101010011000111112. 四位全減器方法一 基于邏輯表達(dá)式一位全減器的真值表如下所示，可得到一位全減器的邏輯表達(dá)式，再將每位級(jí)聯(lián)，采用generate語(yǔ)句可完成四位全減器描述。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity subtracter1 isport( a,b : in std_logic_vect

8、or(3 downto 0); c0 : in std_logic; c1 : out std_logic; sub : out std_logic_vector(3 downto 0);end subtracter1;architecture rtl of subtracter1 issignal ctmp:std_logic_vector(4 downto 0);begin ctmp(0)<= c0; gen1:for i in 0 to 3 generate sub(i)<= a(i) xor b(i) xor ctmp(i); ctmp(i+1)<= (not a(i

9、) and b(i) or (not a(i) and ctmp(i) or (ctmp(i) and b(i); end generate; c1<=ctmp(4);end rtl;* DEVICE SUMMARY *Chip/ Input Output Bidir LCsPOF Device Pins Pins Pins LCs % Utilizedsubtracter1 EPF6010ATC100-1 9 5 0 8 0 %User Pins: 9 5 0 方法二 基于算術(shù)表達(dá)式library ieee;use ieee.std_logic_1164.all;use ieee.st

10、d_logic_unsigned.all;entity subtracter2 isport( a,b : in std_logic_vector(3 downto 0); c0 : in std_logic; c1 : out std_logic; sub : out std_logic_vector(3 downto 0);end subtracter2;architecture rtl of subtracter2 issignal c0plusb,atmp:std_logic_vector(4 downto 0);begin process(a,b,c0) begin atmp<

11、='0'&a; c0plusb<=c0+b; if atmp>=c0plusb then c1<='0' sub<= a - c0plusb; else c1<='1' sub<= "10000"-b-c0+ a; end if; end process;end rtl;* DEVICE SUMMARY *Chip/ Input Output Bidir LCsPOF Device Pins Pins Pins LCs % Utilizedsubtracter2 EPF6010ATC

12、100-1 9 5 0 25 2 %User Pins: 9 5 0 3.四位十進(jìn)制數(shù)顯示電路首先，設(shè)計(jì)一個(gè)帶滅零功能的BCD碼7段譯碼顯示器，輸入rbi為1時(shí)，要求滅零；否則顯示零。rbo為滅零輸出，作為其后的級(jí)聯(lián)顯示器是否滅零的控制信號(hào)。entity sevsegrb isport( rbi:in bit; bcd:in bit_vector(3 downto 0); seg:out bit_vector(6 downto 0); rbo:out bit);end sevsegrb;architecture rtl of sevsegrb isbeginprocess(rbi,bcd)be

13、gin if (bcd="0000" and rbi='1') then -suppress 0 seg<="0000000" rbo<='1' elsif (bcd="0000" and rbi='0') then - display 0 seg<="1111110" rbo<='0' else case bcd is when "0001" => seg<="0110000"

14、; -1 when "0010" => seg<="1101101" -2 when "0011" => seg<="1111001" -3 when "0100" => seg<="0110011" -4 when "0101" => seg<="1011011" -5 when "0110" => seg<="1011111" -6

15、when "0111" => seg<="1110000" -7 when "1000" => seg<="1111111" -8 when "1001" => seg<="1111011" -9 when others => seg<="0000000" -blank end case; rbo <= '0' end if;end process;end rtl;* DEVICE SU

16、MMARY *Chip/ Input Output Bidir LCsPOF Device Pins Pins Pins LCs % Utilizedsevsegrb EPF6010ATC100-1 5 8 0 18 2 %User Pins: 5 8 0 接著，利用該元件設(shè)計(jì)四位十進(jìn)制數(shù)顯示電路。entity sevsegrb_4bit isport( rbi:in bit; bcd1,bcd2,bcd3,bcd4:in bit_vector(3 downto 0); seg1,seg2,seg3,seg4:out bit_vector(6 downto 0); rbo:out bit);e

17、nd sevsegrb_4bit;architecture rtl of sevsegrb_4bit iscomponent sevsegrbport( rbi:in bit; bcd:in bit_vector(3 downto 0); seg:out bit_vector(6 downto 0); rbo:out bit);end component;signal rb:bit_vector(3 downto 1);beginu4:sevsegrb port map ( rbi,bcd4,seg4,rb(1);u3:sevsegrb port map ( rb(1),bcd3,seg3,rb(2);u2:sevsegrb port map (