JH5001二次開發(fā)實(shí)驗(yàn)指導(dǎo)書(老師)／供綜合設(shè)計(jì)參考

1、JH5001二次開發(fā)參考程序（以下所有程序均調(diào)試通過，可作為編程參考）二OO三年一月課程設(shè)計(jì)一、 可變分頻器的實(shí)驗(yàn)TITLE "Counter"SUBDESIGN Counter(%pcm input%FSX_PCM,BCLKT,DT_PCM:INPUT;%m sequence%m_Sequence:INPUT;%SW input%SW7.0:INPUT;%control mode%Error_SEL1.0:INPUT;%MUX output%MUX_DT:OUTPUT;MUX_CLK:INPUT;Error_ind:OUTPUT;%Test m sequence%m_SE

2、L1.0:INPUT;m_test:OUTPUT;Frame_Ind:OUTPUT;)VARIABLEMain_CLK:LCELL;Counter7.0:DFF;Mode1.0:LCELL;Counter_Out:LCELL;%students pust defined variables at here%Counter_Reset:LCELL;Counter_Out_Buff:DFF;BEGINMain_CLK=MUX_CLK;Mode=M_SEL;%INPUT:Main_CLK:input 256KHz clockMode1.0:Control counter modeCounter_Ou

3、t:Counter outputfunction:if Mode=0:Counter_Out=Main_CLK/213;if Mode=1:Counter_Out=Main_CLK/187;if Mode=2:Counter_Out=Main_CLK/156;if Mode=3:Counter_Out=Main_CLK/15;%-students put his program inhereCASE Mode ISWHEN 0 =>Counter_Reset=(Counter=212);WHEN 1 =>Counter_Reset=(Counter=186);WHEN 2 =>

4、;Counter_Reset=(Counter=155);WHEN 3 =>Counter_Reset=(Counter=14);END CASE;Counter.clk=Main_CLK;CASE (Counter_Reset) ISWHEN 0 =>Counter.d=Counter+1;WHEN 1 =>Counter.d=0;END CASE;Counter_Out_Buff.clk=!Main_CLK;CASE Mode ISWHEN 0 =>Counter_Out_Buff.d=(Counter<106);WHEN 1 =>Counter_Out

5、_Buff.d=(Counter<93);WHEN 2 =>Counter_Out_Buff.d=(Counter<78);WHEN 3 =>Counter_Out_Buff.d=(Counter<7);END CASE;Counter_Out=Counter_Out_Buff;-fellowing program can't be rewriteablem_test=Counter_Out;-not used pinMUX_DT=(FSX_PCM,BCLKT,DT_PCM,m_Sequence,SW7.0,Error_SEL1.0,MUX_CLK)=0;

6、(Error_ind,Frame_Ind)=0;END;課程設(shè)計(jì)二、 m序列的產(chǎn)生實(shí)驗(yàn)TITLE "m generating sequence"SUBDESIGN m(%pcm input%FSX_PCM,BCLKT,DT_PCM:INPUT;%m sequence%m_Sequence:INPUT;%SW input%SW7.0:INPUT;%control mode%Error_SEL1.0:INPUT;%MUX output%MUX_DT:OUTPUT;MUX_CLK:INPUT;Error_ind:OUTPUT;%Test m sequence%m_SEL1.0:I

7、NPUT;m_test:OUTPUT;Frame_Ind:OUTPUT;)VARIABLEMain_CLK,Mode1.0:LCELL;Delay_m6.0:DFF;m_Out:LCELL;%students pust defined variables at here%All_Zero:LCELL;BEGINMain_CLK=MUX_CLK;Mode=M_SEL;%INPUT:Main_CLK:input 256KHz clockm_SEL1.0:select output m sequence typeOUTPUT:m_Out:m sequence outputfunction:gener

8、ating m sequencem_SEL=0:m sequence type is (13) m_SEL=1:m sequence type is (23) m_SEL=2:m sequence type is (103) m_SEL=3:m sequence type is (203) %-students put his program inhereAll_Zero=(Delay_m=0);Delay_m.clk=Main_CLK;Delay_m5.0.d=Delay_m6.1;CASE m_SEL ISWHEN 0 =>Delay_m6.d=Delay_m5 $ Delay_m4

9、 $ All_Zero;WHEN 1 =>Delay_m6.d=Delay_m4 $ Delay_m3 $ All_Zero;WHEN 2 =>Delay_m6.d=Delay_m2 $ Delay_m1 $ All_Zero;WHEN 3 =>Delay_m6.d=Delay_m1 $ Delay_m0 $ All_Zero;END CASE;m_out=Delay_m6;-fellowing program can't be rewriteablem_test=m_Out;-not used pinMUX_DT=(FSX_PCM,BCLKT,DT_PCM,m_Se

10、quence,SW7.0,Error_SEL1.0,MUX_CLK)=0;(Error_ind,Frame_Ind)=0;END;課程設(shè)計(jì)三、 噪聲信號的產(chǎn)生TITLE "noise generating"SUBDESIGN Noise(%MUX input%MUX_DR,MUX_CLKR:INPUT;%PCM output%DR_PCM:OUTPUT;FSR,BCLKR:INPUT;%m output%DR_m:OUTPUT;Frame_Ind:OUTPUT;%SW output%SW_Out7.0:OUTPUT;)VARIABLEDelay_m24.0:DFF;PCM_

11、Count3.0,DR_PCM:DFF;BEGIN%input:FSR:PCM frame indicationBCLKR:PCM data input clockOutput:DR_PCM:noise PCM codefunction:this program output noise to PCM decoder%m sequence generating%Delay_m.clk=FSR;Delay_m23.0.d=Delay_m24.1;-200000011Delay_m24.d=Delay_m3 $ Delay_m0 $ (Delay_m=0);%PCM output%PCM_Coun

12、t.d=PCM_Count+1;PCM_Count.clk=BCLKR & FSR;PCM_COunt.clrn=FSR;DR_PCM.clk=!BCLKR;CASE PCM_Count ISWHEN 0 =>DR_PCM.d=Delay_m0;WHEN 1 =>DR_PCM.d=Delay_m1;WHEN 2 =>DR_PCM.d=Delay_m2;WHEN 3 =>DR_PCM.d=Delay_m3;WHEN 4 =>DR_PCM.d=Delay_m4;WHEN 5 =>DR_PCM.d=Delay_m5;WHEN 6 =>DR_PCM.d

13、=Delay_m6;WHEN 7 =>DR_PCM.d=Delay_m7;END CASE;%fellowing program can't be writeable%(DR_m,Frame_Ind)=(MUX_DR,MUX_CLKR)=0);SW_Out7.0=Delay_m7.0;END;課程設(shè)計(jì)四、 復(fù)接實(shí)驗(yàn)TITLE "FRAME"%=MUXplex data defining=%CONSTANT UW=B"11100100"CONSTANT DataA=h"11"CONSTANT DataB=h"22

14、"SUBDESIGN Frame(%pcm input%FSX_PCM,BCLKT,DT_PCM:INPUT;%m sequence%m_Sequence:INPUT;%SW input%SW7.0:INPUT;%control mode%Error_SEL1.0:INPUT;%MUX output%MUX_DT:OUTPUT;MUX_CLK:INPUT;Error_ind:OUTPUT;%Test m sequence%m_SEL1.0:INPUT;m_test:OUTPUT;Frame_Ind:OUTPUT;)VARIABLE%students define variable i

15、n here%Count4.0,load,Send_buff7.0:DFF;MUX_DT:DFF;Send_bit:LCELL;BEGIN%INPUT:MUX_CLK:input multiplex 256KHz clockSW7.0:multiplex data 1 -> 8 bit switch informationDataA:multiplex data A which is define as constantDataB:multiplex data B which is define as constantUW:multiplex data B which is define

16、 as constantoutput:MUX_DT:multiplex data outputFrame_Int:Frame indicationfunction:ultiplexDataA, DataB,SW,UW is combined as one output data stream%=students program put here=%32 byte counter for per frame is 32 bit%Count.clk=MUX_CLK;Count.d=Count+1;Frame_Ind=Count4;%load generating%load.d=(Count=31)

17、 # (Count=7) # (Count=15) # (Count=23);load.clk=!MUX_CLK;%load data%Send_buff.clk=load;CASE (Count4.3) ISWHEN 0 =>Send_Buff.d=UW;WHEN 1 =>Send_Buff.d=DataA;WHEN 2 =>Send_Buff.d=DataB;WHEN 3 =>Send_Buff.d=SW;END CASE;%parallel to serial%CASE Count2.0 ISWHEN 0 =>Send_bit=Send_buff7;WHEN

18、 1 =>Send_bit=Send_buff6;WHEN 2 =>Send_bit=Send_buff5;WHEN 3 =>Send_bit=Send_buff4;WHEN 4 =>Send_bit=Send_buff3;WHEN 5 =>Send_bit=Send_buff2;WHEN 6 =>Send_bit=Send_buff1;WHEN 7 =>Send_bit=Send_buff0;END CASE;MUX_DT.d=Send_bit;MUX_DT.clk=!MUX_CLK;%fellowing can't be rewriteab

19、le%Error_ind=(FSX_PCM,BCLKT,DT_PCM,m_Sequence,Error_SEL1.0,m_SEL)=0;m_test=GND;END;課程設(shè)計(jì)五、 幀同步實(shí)驗(yàn)TITLE "deframe"%=UW define=%CONSTANT UW=B"11100100"SUBDESIGN DeFrame(%MUX input%MUX_DR,MUX_CLKR:INPUT;%PCM output%DR_PCM:OUTPUT;FSR,BCLKR:INPUT;%m output%DR_m:OUTPUT;Frame_Ind:OUTPUT;%S

20、W output%SW_Out7.0:OUTPUT;)VARIABLE%=student variable define=%-serial to parallelstop_Buff7.0:DFF;-load wordLine_Count4.0:DFF;Load_UW,UW_Buff7.0:DFF;Load_DataA,DataA_Buff7.0:DFF;load_DataB,DataB_Buff7.0:DFF;load_SW,SW_Buff7.0:DFF;%detect period counter%Period_Count9.0:DFF;%synchronous%NO_SYN,Reset:D

21、FF;Delay_NO_SYN2.0:DFF;Loss_one_Clock,Hold_Count:LCELL;Error_Word_Count4.0:DFF;Frame_ind:DFF; BEGIN%INPUT:MUX_CLK:input multiplex 256KHz clockMUX_DR:multiplex dataoutput:DataA:multiplex data A which is define as constantDataB:multiplex data B which is define as constantSW:multiplex SWUW:multiplex da

22、ta UWFrame_Ind:receiver frame indicationfunction:demultiplexDataA, DataB,SW,UW is extracted from input data stream%=students program put here=%Clock for m sequence%Frame_ind.d=(Line_Count=0);Frame_ind.clk=!MUX_CLKR;%serial to parallel%stop_Buff7.1.d=stop_Buff6.0;stop_Buff0.d=MUX_DR;stop_Buff.clk=MUX

23、_CLKR;%load word%Line_Count.d=Line_Count+1;Line_Count.clk=(MUX_CLKR & !Loss_one_Clock);-load UW wordload_UW.d=(Line_Count=7);load_UW.clk=!MUX_CLKR;UW_buff.d=stop_Buff;UW_buff.clk=load_UW;-load DataAload_DataA.d=(Line_Count=15);load_DataA.clk=!MUX_CLKR;DataA_buff.d=stop_Buff;DataA_buff.clk=load_D

24、ataA;-load DataBload_DataB.d=(Line_Count=23);load_DataB.clk=!MUX_CLKR;DataB_buff.d=stop_Buff;DataB_buff.clk=load_DataB;-load SWload_SW.d=(Line_Count=31);load_SW.clk=!MUX_CLKR;SW_buff.d=stop_Buff;SW_buff.clk=load_SW;SW_Out=SW_buff;%period counter%Period_Count.d=Period_Count+1;-512 framePeriod_Count.c

25、lk=Load_UW;%synchronous%NO_SYN.d=(Error_Word_Count>30);NO_SYN.clk=load_UW;Reset.d=(period_Count=1);Reset.clk=Load_UW;%loss one clock generating%Delay_NO_SYN2.0.clk=!MUX_CLKR;Delay_NO_SYN2.1.d=Delay_NO_SYN1.0;Delay_NO_SYN0.d=NO_SYN;Loss_one_Clock=(Delay_NO_SYN2 $ Delay_NO_SYN1) & Delay_NO_SYN1

26、;%eror word counter%Error_Word_Count.clrn=!Reset;Error_Word_Count.clk=!load_UW;Hold_Count=(Error_Word_Count=31);CASE (Hold_Count,(UW_Buff=UW) ISWHEN 0 =>Error_Word_Count.d=Error_Word_Count+1;WHEN OTHERS =>Error_Word_Count.d=Error_Word_Count;END CASE;%fellowing program can't be change%(DR_P

27、CM,DR_m)=(FSR,BCLKR)=0) $ (DataA_Buff=0) $ (DataB_Buff=0);END;課程設(shè)計(jì)六、 擾碼實(shí)驗(yàn)TITLE "Scrambler"SUBDESIGN Scrambler(%pcm input%FSX_PCM,BCLKT,DT_PCM:INPUT;%m sequence%m_Sequence:INPUT;%SW input%SW7.0:INPUT;%control mode%Error_SEL1.0:INPUT;%MUX output%MUX_DT:OUTPUT;MUX_CLK:INPUT;Error_ind:OUTPUT;%

28、Test m sequence%m_SEL1.0:INPUT;m_test:OUTPUT;Frame_Ind:OUTPUT;)VARIABLEMain_CLK:LCELL;%students pust defined variables at here%Delay_m6.0:DFF;m_Out:LCELL;All_Zero,Scrambler_Out:LCELL;Delay_Buffer6.0:DFF;BEGINMain_CLK=MUX_CLK;%INPUT:Main_CLK:input 256KHz clockm_SEL1.0:select output m sequence type fo

29、r testOUTPUT:Scrambler_Out:scrambler outputm_test:test Data output%-students put his program inhereAll_Zero=(Delay_m=0);Delay_m.clk=!Main_CLK;Delay_m5.0.d=Delay_m6.1;CASE m_SEL ISWHEN 0 =>Delay_m6.d=Delay_m5 $ Delay_m4 $ All_Zero;WHEN 1 =>Delay_m6.d=VCC;WHEN 2 =>Delay_m6.d=GND;WHEN 3 =>D

30、elay_m6.d=!Delay_m6;END CASE;m_out=Delay_m6;-scrambler:X7+X4+1Delay_Buffer.clk=!Main_CLK;Delay_Buffer5.0.d=Delay_Buffer6.1;Delay_Buffer6.d=Delay_BUffer0 $ Delay_Buffer4 $ m_Out;Scrambler_Out=Delay_Buffer6;-fellowing program can't be rewriteablem_test=m_out;-not used pinMUX_DT=Scrambler_Out;(Erro

31、r_ind,Frame_Ind)=(FSX_PCM,BCLKT,DT_PCM,m_Sequence,SW7.0,Error_SEL1.0,MUX_CLK)=0;END;課程設(shè)計(jì)七、 解擾實(shí)驗(yàn)TITLE "descrambler"SUBDESIGN Descrambler(%MUX input%MUX_DR,MUX_CLKR:INPUT;%PCM output%DR_PCM:OUTPUT;FSR,BCLKR:INPUT;%m output%DR_m:OUTPUT;Frame_Ind:OUTPUT;%SW output%SW_Out7.0:OUTPUT;)VARIABLECLK

32、R,DR:LCELL;%=student variable define=%Delay_Buffer7.0:DFF;Descrambler_Out:LCELL;BEGINCLKR=!MUX_CLKR;DR=MUX_DR;%INPUT:CLKR:input data clockDR:input dataoutput:Descrambler_Out:descrabmler outputscrambler:X7+X4+1%=students program put here=%-scrambler:X7+X4+1Delay_Buffer.clk=CLKR;Delay_Buffer6.0.d=Dela

33、y_Buffer7.1;Delay_Buffer7.d=DR;DeScrambler_Out=Delay_Buffer7 $ Delay_Buffer4 $ delay_Buffer0;%fellowing program can't be change%DR_m=Descrambler_Out;(Frame_Ind,DR_PCM,SW_Out)=(FSR,BCLKR)=0);END;課程設(shè)計(jì)八、 BPSK相位調(diào)實(shí)驗(yàn)TITLE "BPSK generating"SUBDESIGN BPSK(%pcm input%FSX_PCM,BCLKT,DT_PCM:INPUT;

34、%m sequence%m_Sequence:INPUT;%SW input%SW7.0:INPUT;%control mode%Error_SEL1.0:INPUT;%MUX output%MUX_DT:OUTPUT;MUX_CLK:INPUT;Error_ind:OUTPUT;%Test m sequence%m_SEL1.0:INPUT;m_test:OUTPUT;Frame_Ind:OUTPUT;)VARIABLE%=students pust defined variables at here=%Main_CLK,Data_SEL1.0:LCELL;Delay_m2.0:DFF;Da

35、ta,CLKT_Data,BPSK_Out:LCELL;Data01X1.0:DFF;Div_32K2.0:DFF;Carrier_Ref:LCELL;BEGINMain_CLK=MUX_CLK;Data_SEL=M_SEL;%INPUT:Main_CLK:input 256KHz clock which is carrierData_SEL1.0:select output m sequence typeOUTPUT:BPSK_Out:BPSK signal outputdescribing:Data rate is 16Kbpsfunction:Data_SEL=0:01 coder Da

36、ta_SEL=1:0011 coder Data_SEL=2:m1 sequence Data_SEL=3:m2 sequence%=student program put here=%-data clock generatingDiv_32K.clk=Main_CLK;Div_32K.d=Div_32K+1;CLKT_Data=Div_32K2;-test data generatingData01X.clk=!CLKT_Data;Data01X.d=Data01X+1;Delay_m.clk=!CLKT_Data;Delay_m1.0.d=Delay_m2.1;Delay_m2.d=del

37、ay_m0 $ Delay_m1 $ (Delay_m=0);CASE Data_SEL ISWHEN 0 =>-01 coderData=Data01X0;WHEN 1 =>-0011 coderData=Data01X1;WHEN 2 =>-m sequenceData=Delay_m2;WHEN 3 =>Data=GND;END CASE;BPSK_Out=Data $ Main_CLK;Carrier_Ref=Main_CLK;%fellowing program can't be changed%m_test=Data;Error_Ind=BPSK_O

38、ut;Frame_Ind=Carrier_Ref;-not used pinMUX_DT=(FSX_PCM,BCLKT,DT_PCM,m_Sequence,SW7.0,Error_SEL1.0,MUX_CLK)=0;END;課程設(shè)計(jì)九、 QPSK相位調(diào)制實(shí)驗(yàn)TITLE "QPSK generating"SUBDESIGN QPSK(%pcm input%FSX_PCM,BCLKT,DT_PCM:INPUT;%m sequence%m_Sequence:INPUT;%SW input%SW7.0:INPUT;%control mode%Error_SEL1.0:INPUT;%

39、MUX output%MUX_DT:OUTPUT;MUX_CLK:INPUT;Error_ind:OUTPUT;%Test m sequence%m_SEL1.0:INPUT;m_test:OUTPUT;Frame_Ind:OUTPUT;)VARIABLE%=students pust defined variables at here=%Main_CLK,Data_SEL1.0:LCELL;Delay_m2.0:DFF;Data,CLKT_Data,QPSK_Out:LCELL;Data01X1.0:DFF;Div_32K2.0:DFF;Carrier0:LCELL;Carrier3.1:D

40、FF;S_to_P1.0,QPSK_Data1.0:DFF;Symbol_Clock:DFF;Carrier_Ref:LCELL;BEGINMain_CLK=MUX_CLK;Data_SEL=M_SEL;%INPUT:Main_CLK:input 256KHz clock, and carrier is 128KHzData_SEL1.0:select output m sequence typeOUTPUT:QPSK_Out:QPSK signal outputCarrier_Ref:Carrier outputdescribing:Data rate is 32Kbpsfunction:D

41、ata_SEL=0:01 coder Data_SEL=1:0011 coder Data_SEL=2:m1 sequence Data_SEL=3:m2 sequence%=student program put here=%-data clock generatingDiv_32K.clk=Main_CLK;Div_32K.d=Div_32K+1;CLKT_Data=Div_32K2;-test data generatingData01X.clk=!CLKT_Data;Data01X.d=Data01X+1;Delay_m.clk=!CLKT_Data;Delay_m1.0.d=Dela

42、y_m2.1;Delay_m2.d=delay_m0 $ Delay_m1 $ (Delay_m=0);CASE Data_SEL ISWHEN 0 =>-01 coderData=Data01X0;WHEN 1 =>-0011 coderData=Data01X1;WHEN 2 =>-m sequenceData=Delay_m2;WHEN 3 =>Data=GND;END CASE;-carrier generatingCarrier0=Div_32K0;Carrier1.d=Div_32K0;Carrier1.clk=!Main_CLK;Carrier2.d=Ca

43、rrier1;Carrier2.clk=Main_CLK;Carrier3.d=Carrier2;Carrier3.clk=!Main_CLK;Carrier_Ref=Carrier0;Symbol_Clock.d=!Symbol_Clock;Symbol_Clock.clk=!CLKT_Data;S_To_p1.d=S_to_P0;S_To_P0.d=Data;S_to_P.clk=CLKT_Data;QPSK_Data.d=S_to_P;QPSK_Data.clk=Symbol_Clock;CASE QPSK_Data ISWHEN 0 =>QPSK_Out=Carrier0;WHE

44、N 1 =>QPSK_Out=Carrier1;WHEN 2 =>QPSK_Out=Carrier2;WHEN 3 =>QPSK_Out=Carrier3;END CASE;%fellowing program can't be changed%m_test=Data;Error_ind=QPSK_Out;Frame_Ind=Carrier_Ref;-not used pinMUX_DT=(FSX_PCM,BCLKT,DT_PCM,m_Sequence,SW7.0,Error_SEL1.0,MUX_CLK)=0;END;課程設(shè)計(jì)十、 CMI編碼實(shí)驗(yàn)TITLE &quo

45、t;CMI encoder"SUBDESIGN CMI_Encoder(%pcm input%FSX_PCM,BCLKT,DT_PCM:INPUT;%m sequence%m_Sequence:INPUT;%SW input%SW7.0:INPUT;%control mode%Error_SEL1.0:INPUT;%MUX output%MUX_DT:OUTPUT;MUX_CLK:INPUT;Error_ind:OUTPUT;%Test m sequence%m_SEL1.0:INPUT;m_test:OUTPUT;Frame_Ind:OUTPUT;)VARIABLEMain_CLK:LCELL;%students pust defined variables at here%m_Buff2.0:DFF;Input_Buff,State1:DFF;Data_CLKT,Coder_Buff:DFF;