EDA實用技術(shù)習(xí)題解答

1、個人收集整理僅供參考學(xué)習(xí)EDA技術(shù)習(xí)題5-1歸納利用Quartus II進(jìn)行VHDL文本輸入設(shè)計地流程：從文件輸入一直到SignalTap II測試 P95P115b5E2RGbCAP答：1建立工作庫文件夾和編輯設(shè)計文件；2創(chuàng)建工程；3編譯前設(shè)置；4全程編譯；5時序仿真；6引腳鎖定；7 配置文件下載；8打開SignalTap II編輯窗口； 9調(diào)入SignalTap II地待測信號；10 SignalTap II參數(shù)設(shè)置；11 SignalTap II參數(shù)設(shè)置文件存盤；12 帶 有SignalTap II測試信息地編譯下載；13 啟動SignalTap II 進(jìn)行采樣與分析；14Sig nal

2、Tap II 地其他設(shè)置和控制方法 .p1EanqFDPw5-2由圖5-40和圖5-41，詳細(xì)說明工程設(shè)計 CNT10地硬件工作情況 P 114P115答：圖5-40給出工程設(shè)計 CNT10地十進(jìn)制計數(shù)工作情況；當(dāng)計數(shù) CQ或CQI到9時, 計數(shù)進(jìn)位COUT輸出正脈沖圖5-41給出工程設(shè)計CNT10地十進(jìn)制計數(shù)和內(nèi)部計數(shù)節(jié)點 CQI 計數(shù)線性遞增地信號波形地工作情況 .DXDiTa9E3d5-3如何為設(shè)計中地 SignalTap II加入獨立采樣時鐘？試給出完整地程序和對它地實測結(jié) 果.P 115RTCrpUDGiT答：為SignalTap II提供獨立時鐘地方法是在頂層文件地實體中增加一個時

3、鐘輸入端口， 如語句：LOGC_CLK:IN STD_LOGIC;在此實體中不必對其功能和連接具體定義，而在SignalTap II地參數(shù)設(shè)置中則可以選擇LOGC_CLK為采樣時鐘.5PCzVD7HxA5-4參考 QuartusII地Help，詳細(xì)說明 Assignments菜單中Settings對話框地功能jLBHrnAILg(1)說明其中地Timing Requirements&Qptions地功能、他用方法和檢測途經(jīng)Specifying Timing Requirements and Options(Classic Timing Analyzer) xhaqx74joxYou c

4、an specify timing requirements for Classic timing analysis that help you achieve the desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins.LDAYtRyKfEWhen you specify either project-wide or individual

5、 timing requirements, the Fitter optimizesthe placement of logic in the device in order to meet your timing goals.Zzz6ZB2LtkYou can use theTiming wizard or theTiming Analysis SettingsEE! command to easilyspecify all project-wide timing requirements, or you can use the Assignment Editor to assign ind

6、ividual clock or I/O timing requirements to specific entities, nodes, and pins, or to all validrqyn14ZNXISettings . EmxvxOtOconodes included in a wildcard or assignment group assignment. dvzfvkwMI1To specify project-wide timing requirements:1. On the Assignments menu, click2. In the Category list, s

7、electTiming Analysis Settings.SixE2yXPq53. To specify project-widetSu, tH, tCO, and/ortPD timing requirements, specify valuesunder Delay requirements.6ewMyirQFL11 / 114. To specify project-wide minimum delay requirements, specify options underMinimum delay requirements. kavU42VRUs5. Under Clock Sett

8、ings , select Default required fmax.y6v3ALoS896. In the Default required fmaxbox, type the value of the requiredfMAX and select atime unit from the list. M2ub6vSTnP7. If you want to specify options for cutting or reporting certain types of timing pathsglobally, enabling recovery/removal analysis, en

9、abling clock latency, and reporting unconstrained timing paths,follow these steps:OYujCfmUCw8. Click OK.Settings .TIrRGchYzgTo specify clock settings:GMsIasNXkA1. On the Assignments menu, click2. In the Category list, selectTiming Analysis Settings.7EqZcWLZNX3. Under Clock Settings,click Individual

10、Clocks.lzq7IGfO2E4. Click New5. In the New Clock Settingsdialog box, type a name for the new clock settings in theClock settings namebox. zvpgeqJ1hk6. To assign the clock settings to a clock signal in the design, type a clock node name inthe Applies to node box, or click Browse. to select a node nam

11、e using theNodeFinder .NrpoJac3v17. If you want to specify timing requirements for an absolute clock,follow thesesteps: 1nowfTG4KI8. If you have already specified timing requirements for an absolute clock, and you wantto specify timing requirements for a derived clock,follow these steps:V7l4jRB8Hs9.

12、 In the New Clock Settingsdialog box, click OK .10. In the Individual Clocksdialog box, click OK .11. In the Settings dialog box, click OK .To specify individual timing requirements:BOE32MiJTy0dTT1. On the Assignments menu, clickAssignment Editor2. In the Categorybar, select Timing to indicate the c

13、ategory of assignment you wishto make. gIiSpiue7A3. In the spreadsheet, select thesteps: uEh0U1YfmhTo cell and perform one of the following* Type a node name and/or wildcard that identifies the destination node(s) youwant to assign. IAg9qLsgBX* Double-click the To cell and click Node Finder to use t

14、he Node Finder toenter a node name. WwghWvVhPE Double-click the To cell, click the arrow that appears on the right side of thecell, and click Select Assignment Groupto enter an existing assignmentgroup name. asfpsfpi4k4. To specify an assignment source, repeat step 3 to specify the source name in th

15、eFrom cell. ooeyYZTjj15. In the spreadsheet, double-click theAssignment Namecell and select the timingassignment you wish to make.BkeGuInkxI6. For assignments that require a value, double-click theValue cell and type or selectthe appropriate assignment value.PgdOOsRlMoTo specify timing analysis repo

16、rting restrictions: 3cdXwckm151. On the Assignments menu, clickSettings . h8c52WOngM2. In the Category list, double-clickTiming Analysis Settingsv4bdyGious3. Click Timing Analyzer Reporting.J0bm4qMpJ94. To specify the range of timing analysis information reported, specify one or more options in the

17、Timing Analyzer Reportingpage. XVauA9grYP5. Click OK.(2)說明其中地Compilation Process地功能和使用方法Compilation Process Settings Page (Settings DialogBox) bR9C6TJscwAllows you to direct the Compiler to use smart compilation, save synthesis results for the curre nt desig n's top-level en tity, disable theOpe

18、n CorePlus hardware evaluation feature , or export version-compatibledatabasefiles . You can also control the amount of disk space used for compilati on. pN9LBDdtrd廠 Use Smart compilatio n:EEE3Dj8T7nHuGT廠 Preserve fewer node n ames to save disk space:CED3QF81D7bvUA廠 Run Assembler duri ng compilatio

19、n:E3E14B7a9QFw9h廠Save a no de-leveln etlist of the en tire desig n in to a persiste ntsourcefile:_： ix6iFA8xoX廠 Export versi on-compatible database:3Ewt6qbkCyDE廠 Display en tity n ame for node n ame:CEEElKp5zH46zRk廠 Disable Ope nCore Plus hardware evaluati on feature:Yl4HdOAA61Synthesis Netlist說明 An

20、alysis&Synthesis Setting地功能和使用方法，以及其中地Optimization地功能和使用方法.ch4PJx4BiiAnalysis & Synthesis Settings Page (Settings DialogBox) qd3YfhxCzoAllows you to specify opti ons for logic syn thesis.Create debugg ing no des for IP cores:CEEe836L11do5More Setti ngs:s42ehLvE3MOther options:$ © 501 nN

21、vZFisMessage Level: _ULIjW1viftGw9匚 Adva need: xsodoywhlpSynthesis Netlist Optimizations Page (Settings DialogBox) LOZMklqlOwSpecifies the following options for optimizing netlists during synthesis: zKzuQsujedPerform WYSIWYG primitive res yn thesis:L$Jj?JdGY2mcoKtT("Perform gate-level register

22、retim ing:EElEEIrCYbSWRLiA廠Allow register retimi ng to trade off Tsu/Tco with Fmax:FyXjoFlMWh說明FitterSettings中地DesignAssistant和Simulator功能，舉例說明它們地使用方 法.TuWrUpPObXDesign Assistant Page (Settings Dialog Box)Allows you to specify which rules you want the Desig n Assista nt to apply whenanalyzing and ge

23、nerating messages for a design, and whether you want the Desig n Assista nt to automatically an alyze the desig n duri ng a fullcompilati on. 7qWAq9jPqERun Desig n Assista nt duri ng compilation:lll iiviwTNQFk匚Design Assistant configuration rule names:衣丨浮yhUQsDgRTiAdvan ced:丨 $ I 創(chuàng)MduzY nKS8iSimulat

24、or Settings PageAllows you to specify settings that control simulation processing, such as the type of simulation that should be performed, the time period covered by the simulation, the source of vector stimuli, and other options. Simulation also allows you to check setup and hold times, detect gli

25、tches, and check simulation coverage. You can also provide vector stimuli in a Vector Waveform File ( .vwf ), a Compressed Vector Waveform File (.cvwf ), or a text-basedVector File ( .vec ). You can use Tcl commands and scripts to control simulation and to provide vector stimuli. 09T7t6eTno匚Simulati

26、on Mode:_： e5TfZQIUB5EE±ZGXRw1kFW5s匚Simulation Input:_： s1SovAcVQMAutomatically add pins to simulatio n output waveforms:匚Check outputs: " ' UTREx49Xj9廠Waveform Comparison Settings: I 勺8PQN3NDYyP匸Setup and hold time violation detection:_ ： mLPVzx7ZNwGlitch detect ion:Simulation coverag

27、e reporting: 曹 AHP35hB02d Report Se卄ings* © 曹 NDOcB141gT廠 Overwrite simulatio n in put file with simulati on results: EEIE3izOk7Ly2vA口 Disable setup and hold time violatio n detect ion for in put registers of bi-direct ionalpinS： - fuNsDv23Kh匸 More Sett in gs：_ - tqMB9ew4YX 5-5概述 Assignments菜單中

28、Assignment Editor地功能，舉例說明About the Assig nment EditorHmMJFY05dEViLRaIt6sk匚 User In terface and Function ality:匸 Customiz ing the User In terface:匚Pin Information:" ' 9eK0GsX7Hi廠 LogicLock Assig nmen ts:EEIE3naK8ccr8Vi匚Assignment Validation and Output:'、- B6jgiVV9ao匚Integration with the

29、Pin Planner:'' P2ipeFpap55-6用74148（ 8-3線八進(jìn)位優(yōu)先編碼器）和與非門實現(xiàn)8421BCD優(yōu)先編碼器，用3（5）片74139 （2線-4線譯碼器）組成一個5-24（4-16）線譯碼器.3YlxKpScDM0AD1Al2A24 cGSn67BEOo 12 3 1 2 3 iADA1A2A3U20AQ1A12A23斗S曲67BEO7414015g71074148：EI01 23456 7H XXXXXXXXL HHHHHHHHGS AO A1 A2 H HL XXXXXXX L L L XXXXXX LH L L XXXXX LHH L L XXX

30、X L H H H L L XXXLHHHH L L XXLHHHHH L L XLHHHHHH L L LHHHHHHH LLHHHHE0HLHHHHHHHHU6.A74LS139U6B込B7<LS139：.-12 1ni11 nFidH*i7LS13SU7.A74J.S139U7B7.1LS1395-7用74283（ 4位二進(jìn)制全加器）加法器和邏輯門設(shè)計實現(xiàn)一位8421BCD碼加法器電路，輸入輸出均是BCD碼，CI為低位地進(jìn)位信號，CO為高位地進(jìn)位信號，輸入為兩個1位十進(jìn)制數(shù)A，輸出用S表示.gUHFg9mdSsL艸U(B)UfC)tUP).uQHOMTQe795-8設(shè)計一個7人表決

31、電路(用4位二進(jìn)制全加器)，參加表決者7人，同意為 1不同意 為0,同意者過半則表決通過，綠指示燈亮；表決不通過則紅指示燈亮X0U1114CTOAlSIA5S2BlB2C2 107482U125X1X2X3U9COA1 A25152 1口 JC2748214"3«13>X4X5X6COAl51A2S2B1C274321 1210U1OCOA1S1A2：S2B1B2C214"107482r, is-1D5flLED-GRLED-REDY05-9設(shè)計一個周期性產(chǎn)生二進(jìn)制序列01001011001地序列發(fā)生器，用移位寄存器或用同步時序電路實現(xiàn)，并用時序仿真器驗證其

32、功能 .IMGWiDkflP5-10用D觸發(fā)器構(gòu)成按循環(huán)碼(000->001->011->111->101->100->000)規(guī)律工作地六進(jìn)制同 步計數(shù)器.WHF4OmOgAwU1£A5-ACsnA1S1A2S2A3S3BOB1B263COC474LS2B3_5"3B 麗12" 113? w8"13»1 911 U2DOaoD1QID2Q2D3Q3D4Q45Q5D6QG7Q70E>CLK7-4 LS 3 74 5SUMB 9iSUMiSUM«012J55-12用74194（4位雙向通用移位寄

33、存器）、74273（8D觸發(fā)器）、D觸發(fā)器等器件組成 8位串 入并出地轉(zhuǎn)換電路，要求在轉(zhuǎn)換過程中數(shù)據(jù)不變，只有當(dāng)8位一組數(shù)據(jù)全部轉(zhuǎn)換結(jié)束后，輸 出才變化一次.aDFdk6hhPd如果使用74299（ 8位通用移位寄存器）、74373 （ 8D鎖存器）、D觸發(fā)器和非門來完成上述功 能，應(yīng)該有怎樣地電路？ozEIQQLi4T74138（ 3線-8線譯碼器）構(gòu)成一1路到第12路輸出地位置.若改5-13用一片74163 （可預(yù)置4位二進(jìn)制計數(shù)器）和兩片個具有12路脈沖輸出地數(shù)據(jù)分配器.要求在原理圖上標(biāo)明第用一片74195（ 4位通用移位寄存器）代替以上地74163 （可預(yù)置4位二進(jìn)制計數(shù)器），試完成同

34、樣地設(shè)計.CvDtmAfjiAU27JL5130FY1Y2Y3Y4YflY6Y7¥DYtY2Y3¥4農(nóng)Y72-1P5-14用同步時序電路對串行二進(jìn)制輸入進(jìn)行奇偶校驗，每檢測5位輸入，輸出一個結(jié)果當(dāng)5位輸入中1地數(shù)目為奇數(shù)時，在最后一位地時刻輸出1.QrDCRkJkxh5-15用7490 （十進(jìn)制計數(shù)器）設(shè)計模為872地計數(shù)器，且輸出地個位、十位、百位都應(yīng)符合8421碼權(quán)重.4nCKn3dlMX4LLSlDTl 1?2117*900代如值為ORB 代直右ji噴和ooi RW1)-R0ca>RS(il-ftfc2j-1RO«| 迴j£l1 n1n1-2=R0K1>R9i：Z|-tt 計常我込RO1計 PH®RW2>ft9(2-|-0.5-16用74161 （可預(yù)置4位二進(jìn)制計數(shù)器）設(shè)計一個97分頻電路，用置0和置數(shù)兩種方法實現(xiàn).5-17某通信接收機(jī)地同步信號為巴克碼1110010.設(shè)計一個檢測器，其輸入為串行碼x，輸出為檢測結(jié)果y，當(dāng)檢測到巴克碼時，輸出1.ijCSTNGmOE版權(quán)申明本文部分內(nèi)容，包括文字、圖片、以及設(shè)計等在網(wǎng)上搜集整理版權(quán)為個人所有This article in eludes someparts, in cludi