vhdl課程設(shè)計(jì)(電子鐘+鬧鈴)

1、數(shù)字鐘的設(shè)計(jì)一、系統(tǒng)功能概述（一）、系統(tǒng)實(shí)現(xiàn)的功能：1、具有“時(shí)”、“分”、“秒”的十進(jìn)制數(shù)字顯示（小時(shí)從00 23）。2、具有手動(dòng)校時(shí)、校分、校秒的功能。3、有定時(shí)和鬧鐘功能，能夠在設(shè)定的時(shí)間發(fā)出鬧鈴聲。4、能進(jìn)行整點(diǎn)報(bào)時(shí)。從59分50秒起，每隔2秒發(fā)一次低音“嘟”的信號(hào)，連續(xù)5次，最后一次為高音“嘀”的信號(hào)。（二）、各項(xiàng)設(shè)計(jì)指標(biāo)：1、顯示部分采用的6個(gè)LED顯示器，從高位至低位分別顯示時(shí)、分、秒。2、有一個(gè)設(shè)置調(diào)鬧鐘定時(shí)時(shí)間、正常時(shí)間的按鈕，選擇調(diào)的對(duì)象。3、有三個(gè)按鈕分別調(diào)時(shí)、分、秒的時(shí)間。4、有一個(gè)按鈕用作開(kāi)啟/關(guān)閉鬧鈴。5、另外需要兩個(gè)時(shí)鐘信號(hào)來(lái)給系統(tǒng)提供脈沖信號(hào)，使時(shí)鐘和鬧鐘正常工

2、作，分別為1Hz、1kHz的脈沖。二、系統(tǒng)組成以及系統(tǒng)各部分的設(shè)計(jì)1、系統(tǒng)結(jié)構(gòu)描述 /要求：系統(tǒng)（或頂層文件）結(jié)構(gòu)描述，各個(gè)模塊（或子程序）的功能描述；（一） 系統(tǒng)的頂層文件：1、 頂層文件圖：（見(jiàn)下頁(yè)）2、 各模塊的解釋?zhuān)海?）、7個(gè)輸入量clk_1khz、clk_1hz、key_slt、key_alarm、sec_set、min_set、hour_set：其中clk_1khz為鬧鈴模塊提供時(shí)鐘，處理后能產(chǎn)生“嘟”、“嘀”和變化的鬧鈴聲音；clk_1hz為計(jì)時(shí)模塊提供時(shí)鐘信號(hào)，每秒計(jì)數(shù)一次；key_slt選擇設(shè)置對(duì)象：定時(shí)或正常時(shí)間；key_alarm能夠開(kāi)啟和關(guān)閉鬧鈴；sec_set、mi

3、n_set、hour_set用于設(shè)置時(shí)間或定時(shí)，與key_slt相關(guān)聯(lián)。各按鍵輸出為脈沖信號(hào)。（2）、CNT60_A_SEC模塊： 這個(gè)模塊式將clk_1hz這個(gè)時(shí)鐘信號(hào)進(jìn)行60進(jìn)制計(jì)數(shù)，并產(chǎn)生一個(gè)分鐘的觸發(fā)信號(hào)。該模塊能將當(dāng)前計(jì)數(shù)值實(shí)時(shí)按BCD碼的格式輸出。將該輸出接到兩位LED數(shù)碼后能時(shí)時(shí)顯示秒的狀態(tài)。通過(guò)alarm_clk可以選擇設(shè)置對(duì)象為時(shí)間還是定時(shí)值。在設(shè)置時(shí)間模式上，key上的一個(gè)輸入脈沖可以將clk的輸入信號(hào)加一。在設(shè)置定時(shí)模式上，key上的脈沖只修改定時(shí)值，不影響時(shí)間脈沖clk的狀態(tài)。同時(shí)該模塊具有兩個(gè)輸出口out_do、out_di來(lái)觸發(fā)整點(diǎn)報(bào)時(shí)的“嘟”、“嘀”聲音。（3）、

4、CNT60_A_MIN模塊： 這個(gè)模塊式將CNT60_A_SEC的輸出信號(hào)進(jìn)行60進(jìn)制計(jì)數(shù)，并產(chǎn)生一個(gè)時(shí)位的觸發(fā)信號(hào)。該模塊能將當(dāng)前計(jì)數(shù)值實(shí)時(shí)按BCD碼的格式輸出。將該輸出接到兩位LED數(shù)碼后能時(shí)時(shí)顯示分的狀態(tài)。通過(guò)alarm_clk可以選擇設(shè)置對(duì)象為時(shí)間還是定時(shí)值。在設(shè)置時(shí)間模式上，key上的一個(gè)輸入脈沖可以將clk的輸入信號(hào)加一。在設(shè)置定時(shí)模式上，key上的脈沖只修改定時(shí)值，不影響時(shí)間脈沖clk的狀態(tài)。 同時(shí)該模塊具有三個(gè)輸出口out_do、out_di、out_alarm來(lái)觸發(fā)整點(diǎn)報(bào)時(shí)的“嘟”、“嘀”、鬧鈴聲音。（4）、CNT24_A_HOUR模塊： 這個(gè)模塊式將CNT60_A_MIN的

5、輸出信號(hào)做24進(jìn)制計(jì)數(shù)。該模塊能將當(dāng)前計(jì)數(shù)值實(shí)時(shí)按BCD碼的格式輸出。將該輸出接到兩位LED數(shù)碼后能時(shí)時(shí)顯示時(shí)的狀態(tài)。通過(guò)alarm_clk可以選擇設(shè)置對(duì)象為時(shí)間還是定時(shí)值。在設(shè)置時(shí)間模式上，key上的一個(gè)輸入脈沖可以將clk的輸入信號(hào)加一。在設(shè)置定時(shí)模式上，key上的脈沖只修改定時(shí)值，不影響時(shí)間脈沖clk的狀態(tài)。同時(shí)該模塊具有一個(gè)輸出口out_alarm來(lái)觸發(fā)整點(diǎn)報(bào)時(shí)的鬧鈴聲音。（5）、PWM_OUT模塊：該模塊為PWM產(chǎn)生模塊，通過(guò)EN可開(kāi)啟和關(guān)閉PWM輸出。模塊根據(jù)CLK信號(hào)二分頻產(chǎn)生的高低音，并組合，能輸出三種聲音狀態(tài)“嘟”、“嘀”、鬧鈴。而該三種聲音要被秒、分、時(shí)的輸出觸發(fā)才能輸出P

6、WM。（二） 系統(tǒng)各個(gè)模塊的VHDL程序：（1）、CNT60_A_SEC模塊：程序源代碼如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt60_a_sec isport( clk,clr,enb: in std_logic;-clk：時(shí)鐘輸入信號(hào)，clr：清零端，enb：使能端 key: in std_logic;-輸入按鍵脈沖，調(diào)整鬧鈴定時(shí)或時(shí)間 alarm_clk: in std_logic;-1:alarm 0:clk -設(shè)置模式選擇：鬧鈴調(diào)節(jié)模式、時(shí)間調(diào)節(jié)模式 qo

7、ut_sl: out std_logic_vector(3 downto 0); -顯示輸出秒的低位 qout_sh: out std_logic_vector(3 downto 0);-顯示輸出秒的高位 co: out std_logic; -進(jìn)位輸出，觸發(fā)分計(jì)數(shù)模塊 out_do: out std_logic;-在整點(diǎn)報(bào)時(shí)中輸出“嘟”觸發(fā)信號(hào)out_di: out std_logic -在整點(diǎn)報(bào)時(shí)中輸出“嘀”觸發(fā)信號(hào));end;architecture a of cnt60_a_sec issignal qout2_l:std_logic_vector(3 downto 0);signal

8、 qout2_h:std_logic_vector(3 downto 0);signal alarm_l:std_logic_vector(3 downto 0);signal alarm_h:std_logic_vector(3 downto 0);signal clk1,clk2,tclk,aclk,ac_slt: std_logic;beginprocess(alarm_clk) -當(dāng)該端口輸入一個(gè)脈沖時(shí)，修改設(shè)置模式：時(shí)間調(diào)整或鬧鈴模式切換beginif alarm_clk'event and alarm_clk='1' thenif ac_slt='0

9、' then-如果為定時(shí)模式，將改為鬧鈴模式ac_slt<='1'elseac_slt<='0'end if;end if;end process;process(key,clk,ac_slt)-根據(jù)設(shè)置模式，處理key上的脈沖信號(hào)beginif ac_slt='0' then -時(shí)間調(diào)整模式aclk<='0'if clk='1' and key='1' then -clk=1則tclk<=0，通過(guò)挖洞方式添加一個(gè)脈沖tclk<='0'elsif

10、 clk='0' and key='1' then -clk=0,則tclk<=1,產(chǎn)生一個(gè)高電平，添加一脈沖tclk<='1'elsetclk<=clk;end if;elsif ac_slt='1' then -鬧鈴調(diào)整模式tclk<=clk;aclk<=key; -key上的脈沖直接修改鬧鈴定時(shí)值end if;end process;process(tclk,clr,enb) -60進(jìn)制計(jì)數(shù)，個(gè)位、十位放在兩個(gè)臨時(shí)變量中，表示秒的狀態(tài)beginif clr='1' then-cl

11、earing works at the state of high voltageqout2_l<="0000"qout2_h<="0000"elsif tclk'event and tclk='1' thenif enb='1' then-enable works at high voltageif qout2_l="1001" and qout2_h="0101" thenqout2_l<="0000"-a full mode is

12、completed and a carryout is generatedqout2_h<="0000"elsif qout2_l="1001" thenqout2_l<="0000"qout2_h<=qout2_h+1;elseqout2_l<=qout2_l+1;- in process of countingend if;end if;end if;end process; process(aclk,clr,enb)-修改鬧鈴的定時(shí)值beginif clr='1' then-clearin

13、g works at the state of high voltagealarm_l<="0000"alarm_h<="0000"elsif aclk'event and aclk='1' thenif enb='1' then-enable works at high voltageif alarm_l="1001" and alarm_h="0101" thenalarm_l<="0000"-a full mode is compl

14、eted and a carryout is generatedalarm_h<="0000"elsif alarm_l="0101" thenalarm_l<="0000"alarm_h<=alarm_h+1;elsealarm_l<=alarm_l+1;- in process of countingend if;end if;end if;end process; process(qout2_l,qout2_h,alarm_l,alarm_h,alarm_clk)- 產(chǎn)生進(jìn)位,顯示時(shí)間或鬧鈴定時(shí)值begi

15、n if qout2_l="0000" and qout2_h="0000" thenco<='1'else co<='0'end if;if ac_slt='0' then - 顯示時(shí)間qout_sl<=qout2_l;qout_sh<=qout2_h;else - 顯示定時(shí)值qout_sh<=alarm_h;qout_sl<=alarm_l;end if;end process;process(qout2_l,qout2_h) - 根據(jù)秒的狀態(tài)輸出“嘟”、“嘀”觸發(fā)信

16、號(hào)beginif qout2_h="0101" thenif qout2_l="0000" thenout_do<='1'elsif qout2_l="0010" thenout_do<='1'elsif qout2_l="0100" thenout_do<='1'elsif qout2_l="0110" thenout_do<='1'elsif qout2_l="1000" thenou

17、t_do<='1'elseout_do<='0'end if;elsif qout2_h="0000" thenif qout2_l="0000" thenout_di<='1'out_do<='0'else out_di<='0'end if;elseout_do<='0'out_di<='0'end if;end process;end;（2）、CNT60_A_MIN模塊：library ieee;

18、use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt60_a_min isport( clk,clr,enb: in std_logic; -clk：時(shí)鐘輸入信號(hào)，clr：清零端，enb：使能端 key: in std_logic; -輸入按鍵脈沖，調(diào)整鬧鈴定時(shí)或時(shí)間 alarm_clk: in std_logic; -1:alarm 0:clk -設(shè)置模式選擇：鬧鈴調(diào)節(jié)模式、時(shí)間調(diào)節(jié)模式 qout_ml: out std_logic_vector(3 downto 0); -顯示輸出分的低位 qout_m

19、h: out std_logic_vector(3 downto 0); -顯示輸出分的高位 co: out std_logic; -進(jìn)位輸出，觸發(fā)時(shí)計(jì)數(shù)模塊 out_alarm:out std_logic;-鬧鈴觸發(fā)信號(hào)，時(shí)間到后輸出高電平觸發(fā)鬧鈴out_do,out_di: out std_logic-在整點(diǎn)報(bào)時(shí)中輸出“嘟”“嘀”觸發(fā)信號(hào));end;architecture a of cnt60_a_min issignal qout2_l:std_logic_vector(3 downto 0);signal qout2_h:std_logic_vector(3 downto 0);si

20、gnal alarm_l:std_logic_vector(3 downto 0);signal alarm_h:std_logic_vector(3 downto 0);signal clk1,clk2,tclk,aclk,ac_slt: std_logic;beginprocess(alarm_clk) -當(dāng)該端口輸入一個(gè)脈沖時(shí)，修改設(shè)置模式：時(shí)間調(diào)整或鬧鈴模式切換beginif alarm_clk'event and alarm_clk='1' thenif ac_slt='0' then-如果為定時(shí)模式，將改為鬧鈴模式ac_slt<=

21、9;1'elseac_slt<='0'end if;end if;end process;process(key,clk,ac_slt) -根據(jù)設(shè)置模式，處理key上的脈沖信號(hào)beginif ac_slt='0' then -時(shí)間調(diào)整模式aclk<='0'if clk='1' and key='1' then-clk=1則tclk<=0，通過(guò)挖洞方式添加一個(gè)脈沖tclk<='0'elsif clk='0' and key='1' the

22、n-clk=0,則tclk<=1,產(chǎn)生一個(gè)高電平，添加一脈沖tclk<='1'elsetclk<=clk;end if;elsif ac_slt='1' then -鬧鈴調(diào)整模式tclk<=clk;aclk<=key; -key上的脈沖直接修改鬧鈴定時(shí)值end if;end process; process(tclk,clr,enb) -60進(jìn)制計(jì)數(shù)，個(gè)位、十位放在兩個(gè)臨時(shí)變量中，表示分的狀態(tài)beginif clr='1' then-clearing works at the state of high voltag

23、eqout2_l<="0000"qout2_h<="0000"elsif tclk'event and tclk='1' thenif enb='1' then-enable works at high voltageif qout2_l="1001" and qout2_h="0101" thenqout2_l<="0000"-a full mode is completed and a carryout is generatedqou

24、t2_h<="0000"elsif qout2_l="1001" thenqout2_l<="0000"qout2_h<=qout2_h+1;elseqout2_l<=qout2_l+1;- in process of countingend if;end if;end if;end process; process(aclk,clr,enb) -修改鬧鈴的定時(shí)值beginif clr='1' then-clearing works at the state of high voltageala

25、rm_l<="0000"alarm_h<="0000"elsif aclk'event and aclk='1' thenif enb='1' then-enable works at high voltageif alarm_l="1001" and alarm_h="0101" thenalarm_l<="0000"-a full mode is completed and a carryout is generatedalarm_h

26、<="0000"elsif alarm_l="0101" thenalarm_l<="0000"alarm_h<=alarm_h+1;elsealarm_l<=alarm_l+1;- in process of countingend if;end if;end if;end process; process(qout2_l,qout2_h,alarm_l,alarm_h,alarm_clk) - 產(chǎn)生進(jìn)位,顯示時(shí)間或鬧鈴定時(shí)值of high voltagebegin if qout2_l="0000

27、" and qout2_h="0000" thenco<='1'else co<='0'end if;if ac_slt='0' thenqout_ml<=qout2_l;qout_mh<=qout2_h;elseqout_mh<=alarm_h;qout_ml<=alarm_l;end if;end process;process(qout2_l,qout2_h,alarm_l,alarm_h) 判斷定時(shí)值與時(shí)間值相等，輸出鬧鈴觸發(fā)信號(hào)begin if qout2_l=alarm

28、_l and qout2_h=alarm_h thenout_alarm<='1'elseout_alarm<='0'end if;end process;process(qout2_l,qout2_h) - 根據(jù)分的狀態(tài)輸出“嘟”、“嘀”觸發(fā)信號(hào)beginif qout2_l="1001" and qout2_h="0101" thenout_do<='1'elseout_do<='0'end if;if qout2_l="0000" and q

29、out2_h="0000" thenout_di<='1'elseout_di<='0'end if;end process;end;（3）、CNT24_A_HOUR模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt24_a_hour isport( clk,clr,enb: in std_logic; -clk：時(shí)鐘輸入信號(hào)，clr：清零端，enb：使能端 key: in std_logic; -輸入按鍵脈沖

30、，調(diào)整鬧鈴定時(shí)或時(shí)間 alarm_clk: in std_logic;-1:alarm 0:clk-設(shè)置模式選擇：鬧鈴調(diào)節(jié)模式、時(shí)間調(diào)節(jié)模式 qout_hl: out std_logic_vector(3 downto 0); -顯示輸出時(shí)的低位 qout_hh: out std_logic_vector(3 downto 0); -顯示輸出時(shí)的高位 co: out std_logic; -進(jìn)位輸出 out_alarm:out std_logi-鬧鈴觸發(fā)信號(hào)輸出);end;architecture a of cnt24_a_hour issignal qout2_l:std_logic_vec

31、tor(3 downto 0);signal qout2_h:std_logic_vector(3 downto 0);signal alarm_l:std_logic_vector(3 downto 0);signal alarm_h:std_logic_vector(3 downto 0);signal clk1,clk2,tclk,aclk,ac_slt: std_logic;beginprocess(alarm_clk) -當(dāng)該端口輸入一個(gè)脈沖時(shí)，修改設(shè)置模式：時(shí)間調(diào)整或鬧鈴模式切換beginif alarm_clk'event and alarm_clk='1'

32、; thenif ac_slt='0' then-如果為定時(shí)模式，將改為鬧鈴模式ac_slt<='1' elseac_slt<='0'end if;end if;end process;process(key,clk,ac_slt) -根據(jù)設(shè)置模式，處理key上的脈沖信號(hào)beginif ac_slt='0' then -時(shí)間調(diào)整模式aclk<='0'if clk='1' and key='1' then-clk=1則tclk<=0，通過(guò)挖洞方式添加一個(gè)脈沖tc

33、lk<='0'elsif clk='0' and key='1' then-clk=0,則tclk<=1,產(chǎn)生一個(gè)高電平，添加一脈沖tclk<='1'elsetclk<=clk;end if;elsif ac_slt='1' then -鬧鈴調(diào)整模式tclk<=clk;aclk<=key; -key上的脈沖直接修改鬧鈴定時(shí)值end if;end process; process(tclk,clr,enb) -24進(jìn)制計(jì)數(shù)，個(gè)位、十位放在兩個(gè)臨時(shí)變量中，表示時(shí)的狀態(tài)beginif

34、clr='1' then-clearing works at the state of high voltageqout2_l<="0000"qout2_h<="0000"elsif tclk'event and tclk='1' thenif enb='1' then-enable works at high voltageif qout2_l="1001" thenqout2_l<="0000"-a full mode is comple

35、ted and a carryout is generatedqout2_h<=qout2_h+1;elsif qout2_l="0011" and qout2_h="0010" thenqout2_l<="0000"qout2_h<="0000"elseqout2_l<=qout2_l+1;- in process of countingend if;end if;end if;end process; process(aclk,clr,enb) -修改鬧鈴的定時(shí)值beginif clr=

36、'1' then-clearing works at the state of high voltagealarm_l<="0000"alarm_h<="0000"elsif aclk'event and aclk='1' thenif enb='1' then-enable works at high voltageif alarm_l="1001" thenalarm_l<="0000"-a full mode is completed

37、and a carryout is generatedalarm_h<=qout2_h+1;elsif alarm_l="0011" and alarm_h="0010" thenalarm_l<="0000"alarm_h<="0000"elsealarm_l<=alarm_l+1;- in process of countingend if;end if;end if;end process; process(qout2_l,qout2_h,alarm_l,alarm_h,alarm_c

38、lk) - 產(chǎn)生進(jìn)位,顯示時(shí)間或鬧鈴定時(shí)值of high voltagebegin if qout2_l="0000" and qout2_h="0000" thenco<='1'else co<='0'end if;if ac_slt='0' thenqout_hl<=qout2_l;qout_hh<=qout2_h;elseqout_hh<=alarm_h;qout_hl<=alarm_l;end if;end process;process(qout2_l,qout

39、2_h,alarm_l,alarm_h)-定時(shí)值與時(shí)間值相等，則輸出鬧鐘觸發(fā)信號(hào)begin if qout2_l=alarm_l and qout2_h=alarm_h thenout_alarm<='1'elseout_alarm<='0'end if;end process;end;2、系統(tǒng)以及各個(gè)模塊的仿真波形（1）、系統(tǒng)仿真波形：注：由于下面的模塊仿真存在毛刺，導(dǎo)致系統(tǒng)的仿真圖有一定的問(wèn)題。（2）、CNT60_A_SEC模塊：注：在50、52、54、56、58處有嘟觸發(fā)輸出，00處有嘀觸發(fā)輸出等。（3）、CNT60_A_MIN模塊：注：本圖展示了按鍵調(diào)節(jié)時(shí)間值和定時(shí)值的仿真波形（部分仿真圖）。注：該模塊的仿真波形圖，具有嘟、嘀聲音觸發(fā)輸出，定時(shí)與時(shí)間相等時(shí)有鬧鈴觸發(fā)輸出等。（4）、CNT24_A_HOUR模塊注：該模塊的仿真圖，包含按鍵調(diào)整時(shí)間、定時(shí)值，鬧鐘觸發(fā)輸出等。（5）、PWM_OUT模塊（分三段剪切下來(lái)的，展