ds18B20_FPGA(VHDL語言)

1、【精品文檔】如有侵權(quán)，請聯(lián)系網(wǎng)站刪除，僅供學(xué)習(xí)與交流ds18B20_FPGA(VHDL語言).精品文檔.-VHDL語言編寫DS18B20溫度傳感器程序library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ds18B20 is port(clk : in std_logic; -50MHz dq : inout std_logic; rst: in std_logic; LED : out std_logic; LED2 :

2、out std_logic; LED3 : out std_logic; dataout1,dataout2,dataout3 : out std_logic_vector(6 downto 0 ); -數(shù)end ds18B20; architecture Behavioral of ds18B20 is TYPE STATE_TYPE is (RESET,CMD_CC,WRITE_BYTE,WRITE_LOW,WRITE_HIGH,READ_BIT, CMD_44,CMD_BE,WAIT800MS,GET_TMP,WAIT4MS); signal STATE: STATE_TYPE:=RES

3、ET; signal clk_temp : std_logic:=0; signal clk1m : std_logic; -分頻后得到的1M時(shí)鐘 signal cp: std_logic; - 1ms 時(shí)鐘signal w : integer range 0 to 2 :=0; - xian shi shun xu signal write_temp : std_logic_vector(7 downto 0):=00000000; signal TMP : std_logic_vector(11 downto 0); signal tmp_bit : std_logic; signal W

4、RITE_BYTE_CNT : integer range 0 to 8:=0; signal WRITE_LOW_CNT : integer range 0 to 2:=0; signal WRITE_HIGH_CNT : integer range 0 to 2:=0; signal READ_BIT_CNT : integer range 0 to 3:=0; signal GET_TMP_CNT : integer range 0 to 13:=0; signal cnt : integer range 0 to 100_001:=0; signal cnt2 : integer ra

5、nge 0 to 4000001:=0; signal temp : std_logic; signal data_temp0 : std_logic_vector(15 downto 0); signal decimal0 : std_logic_vector(15 downto 0); signal decimal1 : std_logic_vector(15 downto 0); signal decimal2 : std_logic_vector(15 downto 0); signal decimal3 : std_logic_vector(15 downto 0); signal

6、data_temp1 : std_logic_vector(7 downto 0); signal integer0 : std_logic_vector(7 downto 0); signal integer1 : std_logic_vector(7 downto 0); signal integer2 : std_logic_vector(7 downto 0); signal integer3 : std_logic_vector(7 downto 0); signal integer4 : std_logic_vector(7 downto 0); signal integer5 :

7、 std_logic_vector(7 downto 0); signal integer6 : std_logic_vector(7 downto 0); signal sign : std_logic_vector(7 downto 0); signal count : integer range 0 to 51:=0; signal WRITE_BYTE_FLAG : integer range 0 to 4:=0; function dis(num: std_logic_vector) return std_logic_vector isbegin case num is when 0

8、000 = return 1000000; -0 when 0001 = return 1111001; -1 when 0010 = return 0100100; -2 when 0011 = return 0110000; -3 when 0100 = return 0011001; -4 when 0101 = return 0010010; -5 when 0110 = return 0000010; -6 when 0111 = return 1111000; -7 when 1000 = return 0000000; -8 when 1001 = return 0010000;

9、 -9 when 1010 = return 0001000; -A when 1011 = return 0000011; -b when 1100 = return 1000110; -C when 1101 = return 0100001; -d when 1110 = return 0000110; -E when 1111 = return 0001110; -F when others = return 1111111; -mie end case; end dis;begin ClkDivider:process (clk,clk_temp) begin if rising_e

10、dge(clk) then if (count = 24) then count = 0; clk_temp= not clk_temp; else count = count +1; end if; end if; clk1m12000) then n:=0; cp=not cp; end if; end if; end Process; STATE_TRANSITION:process(STATE,clk1m) begin if rising_edge(clk1m) then if(rst=0) then STATE LED2=0;-*- LED3=0 and cnt500) then -

11、 500s的復(fù)位低電平 dq=0;- dq作為輸出 cnt=cnt+1; STATE=500 and cnt510) then -高阻態(tài)再輸入下一級電路的話，對下級電路無任何影響，和沒接一樣,高阻態(tài)可以應(yīng)用在inout端口里面，這樣在inout沒有輸出的時(shí)候就弄個(gè)高阻態(tài)，這樣就其電平就可以由外面的輸入信號決定了dq=Z; cnt=cnt+1; STATE=510 and cnt750) then - 240stemp=dq; - dq作為輸入if(cnt=580) then temp=dq; if(temp=1) then LED=0; else LED=1; end if; end if;

12、cnt=cnt+1; STATE=750) then cnt=0; -計(jì)數(shù)器清零 STATE -跳躍rom指令“CC”LED2=1; LED3=0; write_temp=11001100; STATE case WRITE_BYTE_CNT is when 0 to 7= if (write_temp(WRITE_BYTE_CNT)=0) then STATE=WRITE_LOW; LED3=1; else STATE=WRITE_HIGH; end if; WRITE_BYTE_CNT if (WRITE_BYTE_FLAG=0) then - 第一次寫0XCC完畢 STATE=CMD_4

13、4; WRITE_BYTE_FLAG=1; elsif (WRITE_BYTE_FLAG=1) then -寫0X44完畢 (寫溫度轉(zhuǎn)換指令后沒有讀數(shù)據(jù)？) STATE=RESET; WRITE_BYTE_FLAG=2; elsif (WRITE_BYTE_FLAG=2) then -第二次寫0XCC完畢 STATE=CMD_BE; WRITE_BYTE_FLAG=3; elsif (WRITE_BYTE_FLAG=3) then -寫0XBE完畢 STATE=GET_TMP; WRITE_BYTE_FLAG=0; end if; WRITE_BYTE_CNTSTATE LED3 dq=0;

14、if (cnt=70) then cnt=0; WRITE_LOW_CNT=1; else cnt dq=Z; if (cnt=5) then cnt=0; WRITE_LOW_CNT=2; else cnt STATE=WRITE_BYTE; WRITE_LOW_CNTWRITE_LOW_CNT case WRITE_HIGH_CNT is when 0= dq=0; if (cnt=8) then cnt=0; WRITE_HIGH_CNT=1; else cnt dq=Z; if (cnt=72) then cnt=0; WRITE_HIGH_CNT=2; else cnt STATE=

15、WRITE_BYTE; WRITE_HIGH_CNTWRITE_HIGH_CNT write_temp=01000100; STATE write_temp=10111110; STATE case READ_BIT_CNT is when 0= dq=0; -4s的低電平 if (cnt=4) then READ_BIT_CNT=1; cnt=0; else cnt dq=Z; -4s的高電平 if (cnt=4) then READ_BIT_CNT=2; cnt=0; else cnt dq=Z; TMP_BIT=dq; -12s讀出數(shù)據(jù) ,就是最后一次賦值的結(jié)果。 if (cnt=4)

16、then READ_BIT_CNT=3; cnt=0; else cnt dq=Z; -控制器拉高總線 if (cnt=50) then -讀出數(shù)據(jù)后，等待50us cnt=0; READ_BIT_CNT=0; STATE=GET_TMP; else cntREAD_BIT_CNT case GET_TMP_CNT is when 0 = STATE=READ_BIT; GET_TMP_CNT STATE=READ_BIT; TMP(GET_TMP_CNT-1)=TMP_BIT;-將讀出的每一位數(shù)據(jù)按順序存進(jìn) TMP（0 to 11）里面 GET_TMP_CNT GET_TMP_CNT=0; STATE if (cnt=4000) then -STATE=WAIT4MS;