EDA實(shí)現(xiàn)電子琴的程序

1、實(shí)驗(yàn)十五電子琴設(shè)計(jì)一、音名與頻率的關(guān)系：音樂上的十二平均律規(guī)定：每兩個(gè)八度音之間的頻率相差一倍。在這兩個(gè)八度音之 間，分成十二個(gè)半音，每兩個(gè)相鄰伴音的頻率比為12 2。另外還規(guī)定，音若A的頻率為 440Hz。音名B到C、E到F之間為半音，其余為全音。這樣，可計(jì)算得從A (簡譜的低音 6)到亦(簡譜的高音6)之間每個(gè)音合的頻率為：A (6)： 440Hza (6)： 880Hzal ( 6 ):1760HzB (7): 493.88Hzb (7): 987.76Hzc (1): 523.25Hzcl (1): 1046.50Hzd (2): 587.33Hzdl (2): 1174.66HzC

2、(3): 659.25Hzcl (3): 1318.51Hzf (4): 698.46Hzfl (4): 1396.92Hzg (5): 783.99Hzgl (5): 1567.98Hz二、設(shè)計(jì)要求：設(shè)計(jì)一個(gè)電于琴，要求能演奏音若A到al之間的全部音階。按下一個(gè)鍵，則演奏該音 若，并用數(shù)碼管顯示音名，用發(fā)光二極管指示高、中、低音。三、設(shè)計(jì)提示：本實(shí)驗(yàn)由鍵盤編碼，斉頻輸出譯碼器、分頻器組成。取10MHz信號作為墓準(zhǔn)。以荃準(zhǔn) 頻率除以上述頻率，可得各音君頻率的分頻系數(shù)。注意，為了減少輸出的偶次諧波成分， 呈后輸出應(yīng)為對稱方波。斉頻輸出譯碼器實(shí)質(zhì)上是一個(gè)多路選擇器，根據(jù)鍵盤編碼的輸 出，選擇音階發(fā)

3、生器的不同的預(yù)晝數(shù)，分頻后輸出音頻。分頻器可以為加法計(jì)數(shù)器，以可以為減法計(jì)數(shù)器，計(jì)算預(yù)直數(shù)時(shí)稍有不同，應(yīng)加以注 意。另外，應(yīng)根據(jù)基準(zhǔn)頻率和輸出頻率，來確定計(jì)教器的位數(shù)。設(shè)計(jì)框圖如下圖所示：10MHz時(shí)鐘掃描時(shí)鐘. 按罕輸入、預(yù)W數(shù)選擇碼r劇一 按鍵編m可預(yù)宜汁數(shù)器電于琴框圖四、實(shí)驗(yàn)步驟1、啟動(dòng)1SE集成開發(fā)環(huán)境，創(chuàng)建工程并輸入設(shè)計(jì)源文件。2、對設(shè)計(jì)進(jìn)行時(shí)序仿真，分析設(shè)計(jì)的正確性。3、鎖定引腳，完成設(shè)計(jì)實(shí)現(xiàn)過程。并在實(shí)驗(yàn)輯上連線，利用IMPACT進(jìn)行程序下載。4、在實(shí)驗(yàn)箱上驗(yàn)證電于琴的功能，觀察并記錄實(shí)驗(yàn)結(jié)果五、實(shí)驗(yàn)報(bào)吿l. music的VHDL源程序：library iccc;use iccc

4、.std_logic_l 164.all;mtity music isport(kin： stdogic_vcctor(0 to 15);spk_out: out stdogic;lcd_out: out stdogic_vuctnr(6 d()yvnix)0);index: out std_logic_vcctor(2 down to 0);elk: in stdogic);end music;architecture stru of music iscomponent tone tabp()n(index : in INTEGER rany 0 to 15;toile : out INTE

5、GER range： 0 to 16#3fff#;code : out INTEGER range 0 to 15;high : out STD_LOGIQ_VECT()R(2 D()WNT() 0);end component;component tone genpori(elk : in STD_L()GIC;toile : in integer range 0 to 16#3ff阱；spks:mitSTD_L()GIC);end component;component hcx21cdport(hex : in integer range 0 to 15;led : out STD_L()

6、G】C_VECT()R(6 downs 0);end component;component keybordport(kin : in STD_L()GIC_VECT()R(O to 15);kout: out INTEGER range 0 to 15 );end component;signal kout: integer range 0 to 15;signal tone： INTEGER range 0 to 16#3fff#;signal digit: integer range 0 to 15;beginul: keybord port map (kin=>kin,k()ut

7、=>kout);u2: tone tab port map (indcx=>kout,t()nc=> toile,c(xlc=>digit,high=>indcx);u3: tonegen port map (elk=>dk,t()nc=>t<)iic,spks=>spk_()ut);u4: hcx21cd port map (hcx=>digit,lcd=>lcd_out);end stru;2. hcx21cd 的 VHPL 源程序library I EEE;use IEEESTD_L()GIC_1164加 1；entity

8、 hcx21cd isporl(hex : in integer range 0 to 15;led : out STD_L()G】C_VECT()R(6 downto 0) );end hcx21cd;architecture rtl of hcx21cd issignal data : std_l(>gic_vcct()r(6 donito 0);beginlcd<=n()t data;with hex selectdata<= M1111001M when 1,H0100100H when 2,-2H0110(X)0H when 3, -3H0011001H when

9、4, -4n0010010H when 5, -5H0000010n when 6,-6H1111000n when 7, -7”0000000” when 8,-8H0010000H when 9, -9n0001000H when 10, -AHOOOOOHH when 11, -bH1000110n when 12, CH0100(X)r, when 13,H00()0110H when 14, 一EH0001110H when 15, -F n 1000000” when others; -0end rd;3. keybord 的 VHPL 源程序library 1EE E;use 1

10、EE ESTD_L()GIC_1164 加 1;entity kcvbord isJJporl(kin : in STD_L()GIC_VECT()R(O to 15);kout: out INTEGER range 0 to 15);end kcvbord;architecture rtl of kcvbord isJsignal data:std_l()gic_vcclor(0 to 15);begindata<=kin；proccss(data)beginif data(0)=*0* then kout<=0;clsif data(l)=,0, then kout<=l

11、;clsif data(2)=,0* then kout<=2;clsif data(3)=,0, then kout<=3;clsif data(4)=,0* then kout<=4;clsif data(5)=V then kout<=5;clsif data(6)=,0* then kout<=6;clsif data(7)=,0, then kout<=7;clsif data(8)=,0* then kout<=8;clsif data(9)=,0, then kout<=9;clsif data(10)=l0, then kout&

12、lt;=10;clsif data(ll)=,0, then kout<=l 1;clsif data(12)=l0, then kout<=12;clsif data(13)=t0> then kout<=13;clsif data(14)=,0f then kout<=14;clsif data(15)=l0, then kout<=15;else NULL;end if;end process;end rd;4. tonegtn 的 VHPL 源程序library I EEE;use IEEESTD_L()GIC_1164如 1;entity tone

13、gen isport(elk : in STD_L()GIC;toile : in integer range 0 to 16#3fff;spks:outSTD_LOGIC);end tonegrn；architecture rtl of tonegen issignal fLillspks:std_logic;begingcnspks:pr()ccss(clk,t()nc)variable countl4: integer range 0 to 16#3fff#;std()gic_vuctx)r(O to 13); beginif elk event and clk=*r thenifcou

14、ntl4=16#3Ff倂 then ”111111111111111” thencountl4:=tonc;fullspks<=*r；elsec()untl4:=countl 4+1 ；fullspks<=tOt;end if;end if;end process;dclayspks:proccss(fullspks)variable c()unt2:std_logic;beginif fullspks'event and fullspks=,r thencount2:=not count2;end if;spks<=count2;end process;end rt

15、l;5. tonctab 的 VHDL 源程序library IEEE;use IEEESTD_L()GIC_1164加 1;entity tone tab isport(index : in INTEGER ran使 0 to 15; tone : out INTEGER rangu 0 to 16#3fff#;code : out INTEGER r；uigc 0 to 15;high : out STD_LOGIQ_VECT()R(2 D()TNT() 0);end tonctab;architecture rtl of tone tab isbeginproccss(indcx)beg

16、incase index iswhen 0 =>i()nc<=5021;codc<=6;hi<=H100H;when 1 =>tonc<=6262;code<=7;hi<=M 100M;when 2 = > tone <=6829;code <=1 ;hi <=H010u;when 3 =>tone<=7872;codc<=2;hi<=,t010u;when 4 =>t()nc<=8801;codc<=3;hi<=,010H;when 5 =>ionc<=9226

17、;codc<=4；hi<=M010H;when 6 =>i()nc<=10007;c()dc<=5;high<=H01()H;when 7 =>tonc<=10703;code<=6;hii<=,010H;when 8 =>tonc<=l 1323;codc<=7;high<=H010H;when 9 =>tonc<= 11607;codc<=1 ;high<=M001H;when 10 =>tone<=12129;code<=2;high<=H00r,;when

18、 11 => tonc<=12593;c()dc<=3;high<=H001H;when 12 =>t()nc<=12805;codc<=4;high<=H001H;when 13 =>tone<=13196;codc<=5;high<=H00rf;when 14 =>tonc<=13544;c()dc<=6;high<=M001n;when 15 => t()nc<=16383;c()dc<=0;high<=H001H; when ()THERS=>NULL；end case；end process;end rtl;實(shí)驗(yàn)記錄：1、設(shè)計(jì)記錄表，記錄引腳鎖定與連線情況。ISE軟件實(shí)驗(yàn)箱端口合稱芯片引腳號IO類型編號elkB4InputJOIindcx<0>F9Output1013indcx<l>E9Output1014indcx<2>DllOutput1015kin<0>A4Input102kin<l>05Input103kin<2>C5Input104kin<3>A6Input105kin&l