專用集成電路

1、實(shí)驗(yàn)一 EDA軟件實(shí)驗(yàn)一、實(shí)驗(yàn)?zāi)康模?、掌握Xilinx ISE 9.2的VHDL輸入方法、原理圖文件輸入和元件庫的調(diào)用方法。2、掌握Xilinx ISE 9.2軟件元件的生成方法和調(diào)用方法、編譯、功能仿真和時(shí)序仿真。3、掌握Xilinx ISE 9.2原理圖設(shè)計(jì)、管腳分配、綜合與實(shí)現(xiàn)、數(shù)據(jù)流下載方法。二、實(shí)驗(yàn)器材：計(jì)算機(jī)、Quartus II軟件或xilinx ISE三、實(shí)驗(yàn)內(nèi)容：1、 本實(shí)驗(yàn)以三線八線譯碼器（LS74138）為例，在Xilinx ISE 9.2軟件平臺(tái)上完成設(shè)計(jì)電路的VHDL文本輸入、語法檢查、編譯、仿真、管腳分配和編程下載等操作。下載芯片選擇Xilinx公司的CoolRu

2、nner II系列XC2C256-7PQ208作為目標(biāo)仿真芯片。2、 用1中所設(shè)計(jì)的的三線八線譯碼器（LS74138）生成一個(gè)LS74138元件，在Xilinx ISE 9.2軟件原理圖設(shè)計(jì)平臺(tái)上完成LS74138元件的調(diào)用，用原理圖的方法設(shè)計(jì)三線八線譯碼器（LS74138），實(shí)現(xiàn)編譯，仿真，管腳分配和編程下載等操作。四、實(shí)驗(yàn)步驟：1、三線八線譯碼器（LS 74138）VHDL電路設(shè)計(jì)(1)三線八線譯碼器（LS74138）的VHDL源程序的輸入打開Xilinx ISE 6.2編程環(huán)境軟件Project Navigator，執(zhí)行“file”菜單中的【New Project】命令，為三線八線譯碼器

3、（LS74138）建立設(shè)計(jì)項(xiàng)目。項(xiàng)目名稱【Project Name】為“Shiyan”,工程建立路徑為“C:XilinxbinShiyan1”，其中“頂層模塊類型（Top-Level Module Type）”為硬件描述語言（HDL），如圖1所示。圖1點(diǎn)擊【下一步】，彈出【Select the Device and Design Flow for the Project】對話框，在該對話框內(nèi)進(jìn)行硬件芯片選擇與工程設(shè)計(jì)工具配置過程。圖2完成具體選擇后點(diǎn)擊【下一步】彈出如圖3所示對話框，在該對話框內(nèi)創(chuàng)建文件資源。圖3圖4打開【New Source】標(biāo)簽，彈出如圖4所示對話框在【File】 

4、;標(biāo)簽下對話框內(nèi)寫入用戶自定義的文件名稱，標(biāo)簽【Locatior】下顯示了新定義文件的創(chuàng)建路徑，選中標(biāo)簽【Add to proje】前的對號(hào)標(biāo)記，將新創(chuàng)建的文件74ls138添加到工程 “Shiyan”中。點(diǎn)擊【下一步】，彈出如圖5所示對話框，在此對話框中輸入三線八線譯碼器（LS 74138）的的端口信息。圖5點(diǎn)擊【下一步】彈出【New Source Information】對話框，在該對話框內(nèi)顯示了新建文件的屬性及信息，如圖6所示。圖6點(diǎn)擊【完成】標(biāo)簽結(jié)束新建工程過程。進(jìn)入Xilinx ISE文本編輯方式，在文本框中編輯輸入3線8線譯碼器的VHDL源程序。library IEEE;use I

5、EEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity ls74138 is Port ( G1 : in std_logic;G2 : in

6、std_logic;INP : in std_logic_vector(2 downto 0); Y : out std_logic_vector(7 downto 0);end ls74138;architecture Behavioral of ls74138 isbeginprocess(G1,G2,INP)begin if(G1 and G2)='1') thencase INP is when "000"=>Y<="00000001" when "001"=>Y<="0000

7、0010" when "010"=>Y<="00000100"when "011"=>Y<="00001000"when "100"=>Y<="00010000" when "101"=>Y<="00100000"when "110"=>Y<="01000000" when "111"=>Y<=&

8、quot;10000000"when others=>Y<="00000000" end case;elseY<="00000000"end if;end process;end Behavioral;在VHDL源程序中，G1和G2為兩個(gè)使能控制信號(hào)，INP為命令碼輸入信號(hào)，Y為8位譯碼輸出信號(hào)。（2）、設(shè)計(jì)文件存盤與語法檢查完成程序代碼輸入后單擊高亮“l(fā)s74138-behavioral”標(biāo)簽，此時(shí)工具窗口將顯示 “Process for Source(ls74138-behavioral)”。用鼠標(biāo)右鍵點(diǎn)擊Process窗

9、口中【Check Syntax】標(biāo)簽，點(diǎn)擊運(yùn)行選項(xiàng)，進(jìn)行程序語法檢查，當(dāng)顯示一綠色對號(hào)標(biāo)志時(shí)即表示程序中不存在語法問題?；螂p擊【Synthesize-XST】當(dāng)顯示一綠色對號(hào)標(biāo)志時(shí)即表示程序綜合成功。（3）、仿真文件設(shè)計(jì)為了驗(yàn)證所設(shè)計(jì)電路功能，需要輸入測試文件對電路程序功能進(jìn)行測試。在【Process】菜單中選擇【New Source】選項(xiàng)，即可彈出對話框，選擇【VHDL Test Bench】添加測試向量文件，并將文件添加到LS74138模塊中運(yùn)行行為仿真選項(xiàng)卡【Behavioral Simulation】，在測試向量文件中填寫代碼，完成后保存，Xilinx ISE自動(dòng)調(diào)用ModelSim

10、SE 6.1c仿真平臺(tái)作為仿真工具。運(yùn)行ModelSim SE 6.1c，。在【transcript】窗口中輸入仿真時(shí)間。在波形【W(wǎng)ave】窗口內(nèi)使用按鈕實(shí)現(xiàn)仿真圖的“放大”“縮小”“全局”功能，由圖中時(shí)序及邏輯關(guān)系可知該三線八線譯碼器行為仿真正常。圖11測試向量參考程序如下：- VHDL Test Bench Created from source file ls74138.vhd - - Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector f

11、or the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee that the testbench will bind correctly to the post-implementation - simulation model.-LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;E

12、NTITY ls74138_ls74138_vhd_tb ISEND ls74138_ls74138_vhd_tb;ARCHITECTURE behavior OF ls74138_ls74138_vhd_tb IS COMPONENT ls74138PORT(G1 : IN std_logic;G2 : IN std_logic;INP : IN std_logic_vector(2 downto 0); Y : OUT std_logic_vector(7 downto 0);END COMPONENT;SIGNAL G1 : std_logic;SIGNAL G2 : std_logic

13、;SIGNAL INP : std_logic_vector(2 downto 0);SIGNAL Y : std_logic_vector(7 downto 0);BEGINuut: ls74138 PORT MAP(G1 => G1,G2 => G2,INP => INP,Y => Y);- * Test Bench - User Defined Section *u1:PROCESS wait for 15 us; BEGININP<="010" G1<='0'wait for 15 us; wait for 15

14、us;INP<="011" G1<='1'wait for 15 us; wait for 100 us;INP<="100" G1<='0'wait for 15 us; wait for 15 us;INP<="101" G1<='1'wait for 15 us; wait;INP<="110" END PROCESS u1;wait for 15 us;u2:PROCESSINP<="111"

15、 BEGINwait for 30 us; G2<='0' INP<="000" wait for 15 us;wait; G2<='1'end PROCESS u3; wait for 100 us;- * End Test Bench - User Defined Section * G2<='0'END behavior ; wait for 15 us; G2<='1' wait; END PROCESS u2;u3:PROCESS BEGIN INP<="

16、000" wait for 30 us; INP<="001"（4）芯片管腳定義如前所述添加用戶定義限制文件，運(yùn)行【Assign Package Pins】選項(xiàng)卡，Xilinx ISE將彈出管腳分配窗口，輸入各個(gè)端口管腳位置并保存，完成芯片管腳定義。（5）編譯與綜合圖16 圖17運(yùn)行【Process for Source】中的【Implement Design】（圖16），ISE將自動(dòng)完成編譯并調(diào)用內(nèi)嵌的綜合工具XST完成綜合過程，運(yùn)行結(jié)果如圖17所示。編譯通過后即自動(dòng)生成了電路燒錄下載文件（*.jed）以及資源消耗報(bào)告，通過該報(bào)告即可了解所設(shè)計(jì)電路的資源消

17、耗情況。由圖可知，在三線八線譯碼器（74LS138）的設(shè)計(jì)中使用了8個(gè)宏單元，9個(gè)乘積項(xiàng)，8個(gè)寄存器單元，13個(gè)用戶引腳及5個(gè)功能輸入塊。2、元件的生成、調(diào)用和仿真新建原理圖文件，命名為 “Sch_LS74138”并添加到工程“Shiyan”中。點(diǎn)擊【下一步】完成原理圖文件的創(chuàng)建。在彈出的原理圖編輯框內(nèi)選擇【Symbols】標(biāo)簽，在其目錄列表內(nèi)顯示了所有可用電路器件，其中包括了我們所設(shè)計(jì)的LS74138。雙擊“l(fā)s74138”將其放置到原理圖編輯區(qū)內(nèi)。點(diǎn)擊為器件添加外圍端口。將原理圖文件保存后返回【Xilinx Project Navigator】平臺(tái)，此時(shí)已經(jīng)將程序所設(shè)計(jì)的器件“LS7413

18、8”配置給了原理圖文件“sch_ls74138”。實(shí)驗(yàn)二 組合邏輯電路的VHDL語言實(shí)現(xiàn)一、實(shí)驗(yàn)?zāi)康模?、掌握VHDL語言設(shè)計(jì)基本單元及其構(gòu)成2、掌握用VHDL語言設(shè)計(jì)基本的組合邏輯電路的方法。二、實(shí)驗(yàn)器材：計(jì)算機(jī)、Quartus II軟件或Xilinx ISE三、實(shí)驗(yàn)內(nèi)容：1、以四選一選擇器為例，在Xilinx ISE軟件平臺(tái)上完成設(shè)計(jì)電路的VHDL文本輸入，編輯，編譯，仿真，管腳分配和編程下載等操作。四、實(shí)驗(yàn)步驟：（一）、用VHDL語言實(shí)現(xiàn)四選一選擇器的設(shè)計(jì)并實(shí)現(xiàn)功能仿真。選擇器常用于信號(hào)的切換，四選一選擇器可以用于4路信號(hào)的切換。其真值表如下所示： 表3 四選一真值表選擇輸入數(shù)據(jù)輸入數(shù)據(jù)

19、輸出baInput0Input1Input2Input3y000xxx0001xxx101x0xx001x1xx110xx0x010xx1x111xxx0011xxx11用VHDL語言實(shí)現(xiàn)四選一選擇器的設(shè)計(jì)并實(shí)現(xiàn)功能仿真。參考程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4 IS PORT (INPUT:IN STD_LOGIC_VECTOR (3 DOWNTO 0);A,B:IN STD_LOGIC;Y:OUT STD_LOGIC);END mux4;ARCHITECTURE rt1 OF mux4 ISSIGNAL se1:

20、STD_LOGIC_VECTOR (1 DOWNTO 0);BEGIN se1<=B&A; PROCESS (INPUT,se1) BEGIN IF(se1="00")THEN y<=INPUT(0); ELSIF(se1="01")THEN y<=INPUT(1); ELSIF(se1="10")THEN y<=INPUT(2); ELSE y<=INPUT(3); END IF; END PROCESS;END rt1;測試向量程序如下：- VHDL Test Bench Created fr

21、om source file mux4.vhd - Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee that the testbench will b

22、ind correctly to the post-implementation - simulation model.LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY mux4_mux4_vhd_tb ISEND mux4_mux4_vhd_tb;ARCHITECTURE behavior OF mux4_mux4_vhd_tb IS COMPONENT mux4PORT(INPUT : IN std_logic_vector(3 downto 0);A : IN std_logic;B : IN

23、 std_logic; Y : OUT std_logic);END COMPONENT;SIGNAL INPUT : std_logic_vector(3 downto 0);SIGNAL A : std_logic;SIGNAL B : std_logic;SIGNAL Y : std_logic;BEGINuut: mux4 PORT MAP(INPUT => INPUT,A => A,B => B,Y => Y);- * Test Bench - User Defined Section *u1: PROCESS BEGINA<='0' B

24、<='1'wait for 15us;wait for 5 us;A<='1' B<='0'wait for 15us;wait for 5 us;A<='0' B<='1'wait for 5us;wait;A<='1'end process u2;wait for 5 us;u3: processA<='0'beginwait; INPUT<="1101" END PROCESS u1;wait for 10us

25、;u2: process INPUT <="1010" beginwait for 10us;B<='0' INPUT <="0111" wait for 10us;wait for 20us;B<='1' INPUT <="0001" wait for 20us;wait for 10us;B<='0' INPUT<="0010" wait for 5us;wait ; end process u3; - * End Tes

26、t Bench - User Defined Section *END behavior;仿真結(jié)果如下圖：實(shí)驗(yàn)三 時(shí)序邏輯電路的VHDL語言實(shí)驗(yàn)一、實(shí)驗(yàn)?zāi)康模?、掌握用VHDL語言設(shè)計(jì)基本的時(shí)序邏輯電路及仿真。2、掌握VHDL順序語句和并行語句的異同3、掌握觸發(fā)器同步復(fù)位和異步復(fù)位的實(shí)現(xiàn)方式。4、掌握軟件時(shí)鐘的加入方法。二、實(shí)驗(yàn)器材：計(jì)算機(jī)、Quartus II軟件或xilinx ISE三、實(shí)驗(yàn)內(nèi)容：1、設(shè)計(jì)帶使能的遞增計(jì)數(shù)器2、在步驟1的基礎(chǔ)上設(shè)計(jì)一帶使能的同步（異步）復(fù)位的遞增（遞減）計(jì)數(shù)器四、實(shí)驗(yàn)步驟：參考程序：library ieee;use ieee.std_logic_1164.a

27、ll;use ieee.std_logic_unsigned.all;entity ycounter is port(clk,clear,ld,enable:in std_logic; d:in std_logic_vector(7 downto 0); qk:out std_logic_vector(7 downto 0);end ycounter;architecture a_ycounter of ycounter isbegin PROCESS (clk) VARIABLE cnt :std_logic_vector(7 downto 0); BEGIN IF (clk'EVE

28、NT AND clk = '1') THEN IF(clear = '0') THEN cnt := "00000000"ELSE IF(ld = '0') THENcnt := d;ELSEIF(enable = '1') THENcnt := cnt + "00000001"END IF; END IF;END IF;END IF;qk <= cnt; END PROCESS;end a_ycounter;測試向量如下：- VHDL Test Bench Created from

29、source file ycounter.vhd - 16:50:55 03/24/2008- Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee tha

30、t the testbench will bind correctly to the post-implementation - simulation model.LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY ycounter_a_ycounter_vhd_tb ISEND ycounter_a_ycounter_vhd_tb;ARCHITECTURE behavior OF ycounter_a_ycounter_vhd_tb IS COMPONENT ycounterPORT(clk : I

31、N std_logic;clear : IN std_logic;ld : IN std_logic;enable : IN std_logic;d : IN std_logic_vector(7 downto 0); qk : OUT std_logic_vector(7 downto 0);END COMPONENT;constant clk_cycle: time:=20 us;SIGNAL clk : std_logic;SIGNAL clear : std_logic;SIGNAL ld : std_logic;SIGNAL enable : std_logic;SIGNAL d :

32、 std_logic_vector(7 downto 0);SIGNAL qk : std_logic_vector(7 downto 0);BEGINuut: ycounter PORT MAP(clk => clk,clear => clear,ld => ld,enable => enable,d => d,qk => qk);- * Test Bench - User Defined Section *u1 : PROCESSwait for clk_cycle/2; BEGINclk<='1' clk<='0&#

33、39;wait for clk_cycle/2;wait for clk_cycle/2;clk<='0'clk<='1'wait for clk_cycle/2;wait for clk_cycle/2;clk<='1'clk<='0'wait ;wait for clk_cycle/2;END PROCESS u1;clk<='1'u2: processwait for clk_cycle/2;beginclk<='0'clear<='0'

34、;wait for clk_cycle/2;wait for clk_cycle;clk<='1'clear<='1'wait for clk_cycle/2;wait;clk<='0'end process;wait for clk_cycle/2;u3: processclk<='1'beginwait for clk_cycle/2;ld<='1'clk<='0'wait for clk_cycle*6;wait for clk_cycle/2;ld<

35、='0'clk<='1'wait ;wait for clk_cycle/2;end process u3;clk<='0'u4: processwait for clk_cycle/2;beginclk<='1'enable<='1'wait for clk_cycle/2;wait ;clk<='0'end process u4;u5: process begin d<="00001111" wait; end process u5; -

36、* End Test Bench - User Defined Section *END behavior;仿真結(jié)果如圖所示：實(shí)驗(yàn)四 VHDL層次化設(shè)計(jì)方法實(shí)驗(yàn)一、實(shí)驗(yàn)?zāi)康模?、掌握用VHDL語言層次化設(shè)計(jì)的基本方法。2、掌握GENERATE語句的用法。二、實(shí)驗(yàn)器材：計(jì)算機(jī)、Quartus II軟件或xilinx ISE三、實(shí)驗(yàn)內(nèi)容：設(shè)計(jì)一8位異步計(jì)數(shù)器，它的上一位計(jì)數(shù)器的輸出作為下一位計(jì)數(shù)器的時(shí)鐘信號(hào)，一級(jí)一級(jí)串行連接構(gòu)成一個(gè)異步計(jì)數(shù)器。各個(gè)D觸發(fā)器模塊采用VHDL語言編寫，分別用原理圖和VHDL語言元件例化語句的方法實(shí)現(xiàn)8位異步計(jì)數(shù)器的設(shè)計(jì)。四、實(shí)驗(yàn)步驟：（一）、在原理圖中調(diào)用VHDL生成

37、的D觸發(fā)器模塊實(shí)現(xiàn)8位異步計(jì)數(shù)器的設(shè)計(jì) 1、在xilinx ISE環(huán)境中新建vhdl文本編輯文件，設(shè)計(jì)帶清零端的D觸發(fā)器并編譯仿真。 2、將步驟1所設(shè)計(jì)的D觸發(fā)器生成一個(gè)元件。3、新建原理圖文件，調(diào)用步驟2所生成的D觸發(fā)器元件，在原理圖中實(shí)現(xiàn)8位異步計(jì)數(shù)器。（二）、用VHDL的COMPONENT語句調(diào)用VHDL生成的D觸發(fā)器模塊實(shí)現(xiàn)8位異步計(jì)數(shù)器設(shè)計(jì)。 1、在xilinx ISE環(huán)境中新建vhdl文本編輯文件，設(shè)計(jì)帶清零端的D觸發(fā)器并編譯仿真。2、在同一個(gè)程序中用COMPONENT語句實(shí)現(xiàn)8位異步計(jì)數(shù)器的設(shè)計(jì)。library IEEE;use IEEE.STD_LOGIC_1164.ALL;u

38、se IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity dff isport ( d,clk,clear: in std_logic; q,q_n: out std_logic );end d

39、ff;architecture Behavioral of dff isbeginprocess(clk,clear)beginif (clear='0') then q<='0'elsif(clk'event and clk='1') then q<=d; q_n<=not d;end if;end process;end Behavioral;D觸發(fā)器測試向量程序如下：Test Bench Created from source file dff.vhd - - Notes: - This testbench has

40、 been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee that the testbench will bind correctly to the post-implementation - simulation

41、 model.-LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY dff_dff_vhd_tb ISEND dff_dff_vhd_tb;ARCHITECTURE behavior OF dff_dff_vhd_tb IS COMPONENT dffPORT(d : IN std_logic;clear: in std_logic;clk : IN std_logic; q : OUT std_logic;q_n: out std_logic);END COMPONENT;SIGNAL d : st

42、d_logic;signal clear: std_logic;SIGNAL clk : std_logic;SIGNAL q : std_logic;signal q_n: std_logic;BEGINuut: dff PORT MAP(d => d,clear=>clear,clk => clk,q => q,q_n=> q_n);u1: PROCESS BEGINclk<='0'wait for 5us;clk<='1'wait for 5us;clk<='0'wait for 5us;cl

43、k<='1'wait for 5us;clk<='0'wait for 5us;clk<='1'wait for 5us;clk<='0'wait for 5us;clk<='1'wait for 5us;clk<='0'wait for 5us;clk<='1'wait;end process u1;u2: processbegind<='0'wait for 15us;d<='1' wait f

44、or 25us; d<='0' wait ;end process u2;u3: processbeginclear<='1' wait for 35us;clear<='0'wait for 10us; clear<='1' wait ; end process u3; - * End Test Bench - User Defined Section *END behavior;程序仿真如下圖：新建原理圖文件，調(diào)用步驟1所生成的D觸發(fā)器元件，在原理圖中實(shí)現(xiàn)8位異步計(jì)數(shù)器：end Behavioral;L

45、IBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY rplcont ISPORT(clk,clr:in std_logic; count:out std_logic_vector(7 downto 0);END rplcont;ARCHITECTURE rtl OF rplcont ISsignal count_in_bar:std_logic_vector(8 downto 0);component dffrport(clk,clr,d:in std_logic; q,qb:out std_logic);end component;begincoun

46、t_in_bar(0)<=clk;gen1:for i in 0 to 7 generateu:dffr port map(clk=>count_in_bar(i),clr=>clr,d=>count_in_bar(i+1),q=>count(i),qb=>count_in_bar(i+1);end generate;end rtl;（三） 測試向量設(shè)計(jì)Test Bench Created from source file dff.vhd - - Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee that the testbench will bind correctly to the post-implementation - simulation model.-LIBRAR