基于FPGA數(shù)字秒表設(shè)計

1、目錄1.秒表設(shè)計要求12.設(shè)計思路12.1功能模塊12.1.1分頻器12.1.2計數(shù)器12.1.3數(shù)據(jù)鎖存器12.1.4控制器12.1.5掃描顯示的控制電路22.1.6顯示電路32.1.7按鍵消抖電路33.電路實現(xiàn)44.程序仿真104.1分頻器104.1.1計數(shù)器電路綜合114.1.2計數(shù)器電路仿真114.2同步計數(shù)器134.2.1計數(shù)器實現(xiàn)134.2.2計數(shù)器仿真154.2.3同步計數(shù)器電路綜合174.3按鍵消抖電路184.3.1按鍵消抖電路實現(xiàn)184.3.2按鍵消抖電路仿真184.3.3按鍵消抖電路綜合204.4八段譯碼器204.4.1八段譯碼器實現(xiàn)204.4.2八段譯碼器仿真214.4.

2、3八段譯碼器電路綜合224.5控制器234.5.1控制器234.5.1控制器仿真244.5.3控制器電路綜合255.2View Technology Schematic ：265.3管腳鎖定：276.實驗結(jié)論271.秒表設(shè)計要求（1） 秒表的計時范圍為00：00：00 59：59：99。（2） 兩個按鈕開關(guān)Start/Stop和Split/Reset，控制秒表的啟動、停止、分段和復(fù)位：在秒表已經(jīng)被復(fù)位的情況下，按下“Start/Stop”鍵，秒表開始計時。在秒表正常運行的情況下，如果按下“Start/Stop”鍵，則秒表暫停計時；再次按下該鍵，秒表繼續(xù)計時。在秒表正常運行的情況下，如果按下“S

3、plit/Reset”鍵，顯示停止在按鍵時的時間，但秒表仍然在計時；再次按下該鍵，秒表恢復(fù)正常顯示。在秒表暫停計時的情況下，按下“Split/Reset”鍵，秒表復(fù)位歸零。2.設(shè)計思路2.1功能模塊2.1.1分頻器對晶體振蕩器產(chǎn)生的時鐘信號進行分頻，產(chǎn)生時間基準(zhǔn)信號2.1.2計數(shù)器對時間基準(zhǔn)脈沖進行計數(shù)，完成計時功能2.1.3數(shù)據(jù)鎖存器鎖存數(shù)據(jù)使顯示保持暫停2.1.4控制器通過產(chǎn)生鎖存器的使能信號來控制計數(shù)器的運行、停止以及復(fù)位設(shè)計分析：2.1.5掃描顯示的控制電路 包括掃描計數(shù)器、數(shù)據(jù)選擇器和7段譯碼器，控制8個數(shù)碼管以掃描方式顯 示計時結(jié)果，原理圖如下：實驗電路板上的按鍵2.1.6顯示電路

4、2.1.7按鍵消抖電路消除按鍵輸入信號抖動的影響，輸出單脈沖實驗板上的數(shù)碼管為共陽LED數(shù)碼管按鍵按下時，F(xiàn)PGA的輸入為低電平；松開按鍵時，F(xiàn)PGA的輸入為高電平但是在按下按鍵和松開按鍵的瞬間會出現(xiàn)抖動現(xiàn)象2.2電路框圖3.電路實現(xiàn)- Company: - Engineer: - - Create Date: 09:08:39 03/12/2011 - Design Name: - Module Name: stopwatch_1 - Behavioral - Project Name: - Target Devices: - Tool versions: - Description: -

5、Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: -library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-us

6、e UNISIM.VComponents.all;entity stopwatch_1 isPort (Clk : in STD_LOGIC;start_stop : in STD_LOGIC;split_reset : in STD_LOGIC;ncs : out STD_LOGIC;s : out STD_LOGIC_VECTOR(2 downto 0);seg : out STD_LOGIC_VECTOR (7 downto 0);end stopwatch_1;architecture Behavioral of stopwatch_1 issignal k1,k2,k3,k4: ST

7、D_LOGIC;signal cnt_1,cnt_2 : STD_LOGIC_VECTOR(1 downto 0);signal start_stop_out,split_reset_out: STD_LOGIC;signal count: STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');signal clk_1k: STD_LOGIC;signal z0,z1,z2,z3,z4,z5,z6,q1,q2,q3,q4,q5,q6 : STD_LOGIC_VECTOR(3 downto 0):=(others=>'0&#

8、39;);signal count_2: STD_LOGIC_VECTOR(2 downto 0 ):=(others=>'0');signal in_7: STD_LOGIC_VECTOR(3 downto 0);signal sreg: STD_LOGIC_VECTOR(2 downto 0):="111"signal snext: STD_LOGIC_VECTOR(2 downto 0);Begin-為三八譯碼器置入使能信號 ncs <= '0'-分頻電路process(clk)beginif rising_edge(clk

9、) thenif count = 47999 thencount <=(others=>'0');elsecount <= count+1;end if;end if;end process;clk_1k <= count(15);-同步計數(shù)電路process(clk_1k,sreg(2)beginif rising_edge(clk_1k) thenif sreg(2) = '1' then z0<=(others=>'0');z1<=(others=>'0');z2<=(o

10、thers=>'0');z3<=(others=>'0');z4<=(others=>'0');z5<=(others=>'0');z6<=(others=>'0');elsif sreg(1) = '1' thenz0 <= z0+1;if z0 = 9 thenz0 <=(others=>'0');z1 <= z1+1;if z1 = 9 thenz1 <=(others=>'0&#

11、39;);z2 <= z2+1;if z2 = 9 thenz2 <=(others=>'0');z3 <= z3+1;if z3 = 9 thenz3 <= (others=>'0');z4 <= z4+1;if z4 = 5 thenz4 <= (others=>'0');z5 <= z5+1;if z5 = 9 thenz5 <= (others=>'0');z6 <= z6+1;if z6 = 5 thenz6 <= (others=>

12、;'0');end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;-掃描計數(shù)器process(clk_1k)beginif rising_edge(clk_1k) thencount_2 <= count_2+1;end if;end process;s <= count_2;-鎖存器process(sreg(0),z1,z2,z3,z4,z5,z6)beginif sreg(0) = '1' thenq1 <= z1;q2 <= z2;q3

13、<= z3;q4 <= z4;q5 <= z5;q6 <= z6;end if;end process;-process(count_2,q1,q2,q3,q4,q5,q6)begincase count_2 iswhen "000" => in_7 <= q1;when "001" => in_7 <= q2;when "011" => in_7 <= q3;when "100" => in_7 <= q4;when "110&qu

14、ot; => in_7 <= q5;when "111" => in_7 <= q6;when others => in_7 <= "1111" end case;end process;-八段譯碼器process(in_7)begincase in_7 iswhen "0000" => seg <="00000011"when "0001" => seg <="10011111"when "0010&qu

15、ot; => seg <="00100101"when "0011" => seg <="00001101"when "0100" => seg <="10011001"when "0101" => seg <="01001001"when "0110" => seg <="01000001"when "0111" => seg &

16、lt;="00011111"when "1000" => seg <="00000001"when "1001" => seg <="00001001"when others => seg <="11111101"end case;end process;-按鍵去抖電路process(clk_1k,start_stop)beginif clk_1k'event and clk_1k='0' thenifcnt_1 =

17、 3 thenk1 <= '1'elsek1 <= '0'cnt_1 <= cnt_1+1;end if;k2 <= k1;end if;if start_stop = '0' thencnt_1 <= "00"end if;end process;start_stop_out <= not k1 and k2; process(clk_1k,split_reset)beginif clk_1k'event and clk_1k='0' thenifcnt_2 = 3

18、 thenk3 <= '1'elsek3 <= '0'cnt_2 <= cnt_2+1;end if;k4 <= k3;end if;if split_reset = '0' thencnt_2 <= "00"end if;end process;split_reset_out <= not k3 and k4;-控制器 process(clk_1k,start_stop_out,split_reset_out)beginif rising_edge(clk_1k) thensreg <

19、;= snext;end if;end process;process(start_stop_out,split_reset_out,sreg)begincase sreg iswhen "111" =>if start_stop_out = '1' and split_reset_out = '0' then snext <= "011"else snext <= sreg;end if; when "011" =>if start_stop_out = '1'

20、 and split_reset_out = '0' then snext <= "001"elsif start_stop_out = '0' and split_reset_out = '1' then snext <= "010"else snext <= sreg;end if;when "001" =>if start_stop_out = '0' and split_reset_out = '1' then snext

21、<= "111"elsif start_stop_out = '1' and split_reset_out = '0' then snext <= "011"else snext <= sreg;end if;when "010" =>if start_stop_out = '0' and split_reset_out = '1' then snext <= "011"else snext <= sreg;end

22、 if;when others =>snext <= "111"end case;end process;end Behavioral;注：控制器設(shè)計時，巧妙地將狀態(tài)編碼和控制器輸出的控制信號編碼合二為一，即狀態(tài)編碼也是控制信號編碼，使得程序形式上更為簡單、清晰。4.程序仿真4.1分頻器entity fp is Port ( clk_48M : in STD_LOGIC; clk_1k : out STD_LOGIC);end fp;architecture Behavioral of fp issignal count: STD_LOGIC_VECTOR(15

23、 downto 0):=(others=>'0');beginprocess(clk_48M)beginif rising_edge(clk_48M) thenif count = 47999 thencount <= (others=>'0');elsecount <= count+1;end if;end if;end process;clk_1k <= count(15);end Behavioral;tb : PROCESSBEGINclk_48M <= '1' wait for 10.4 ns;clk

24、_48M <= '0' wait for 10.4 ns;END PROCESS;4.1.1計數(shù)器電路綜合4.1.2計數(shù)器電路仿真由圖可得分頻后的信號周期T=999333718ps0.001s 即的到了1KHz的信號由圖可得時鐘信號周期T=20845ps20.845ns 即的到了48MHz的時鐘信號4.2同步計數(shù)器4.2.1計數(shù)器實現(xiàn)entity count_6 is Port ( clk_1k : in STD_LOGIC; d1 : out STD_LOGIC_VECTOR(3 downto 0); d2 : outSTD_LOGIC_VECTOR(3 downto

25、0); d3 : out STD_LOGIC_VECTOR(3 downto 0); d4 : out STD_LOGIC_VECTOR(3 downto 0); d5 : out STD_LOGIC_VECTOR(3 downto 0); d6 : out STD_LOGIC_VECTOR(3 downto 0);end count_6;architecture Behavioral of count_6 issignal z0,z1,z2,z3,z4,z5,z6: STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');signal c

26、lr,en: STD_LOGIC;Beginclr <= '0' -清零無效en <= '1' -計數(shù)使能有效d1 <= z1;d2 <= z2;d3 <= z3;d4 <= z4;d5 <= z5;d6 <= z6;process(clk_1k,clr)beginif rising_edge(clk_1k) thenif clr = '1' then z0<=(others=>'0');z1<=(others=>'0');z2<=(ot

27、hers=>'0');z3<=(others=>'0');z4<=(others=>'0');z5<=(others=>'0');z6<=(others=>'0');elsif en = '1' thenz0 <= z0+1;if z0 = 9 thenz0 <=(others=>'0');z1 <= z1+1;if z1 = 9 thenz1 <=(others=>'0');z

28、2 <= z2+1;if z2 = 9 thenz2 <=(others=>'0');z3 <= z3+1;if z3 = 9 thenz3 <= (others=>'0');z4 <= z4+1;if z4 = 5 thenz4 <= (others=>'0');z5 <= z5+1;if z5 = 9 thenz5 <= (others=>'0');z6 <= z6+1;if z6 = 5 thenz6 <= (others=>'

29、0');end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;end Behavioral;4.2.2計數(shù)器仿真tb : PROCESSBEGINclk_1k <= '0'wait for 0.5 ms;clk_1k <= '1'wait for 0.5 ms;END PROCESS;0.01s位由圖可以看出為十進制0.1s位由圖可以看出為十進制1s位由圖可以看出為十進制10s位由圖可以看出為六進制1min位由圖可以看出為十進制10min位由圖可以

30、看出為六進制4.2.3同步計數(shù)器電路綜合 4.3按鍵消抖電路4.3.1按鍵消抖電路實現(xiàn)entity quedou is Port ( clk_1k : in STD_LOGIC; key_in : in STD_LOGIC; key_out : out STD_LOGIC);end quedou;architecture Behavioral of quedou issignal k1,k2: STD_LOGIC;signal cnt_1: STD_LOGIC_VECTOR(1 downto 0);beginprocess(clk_1k,key_in)beginif clk_1k'ev

31、ent and clk_1k='0' thenifcnt_1 = 3 thenk1 <= '1'elsek1 <= '0'cnt_1 <= cnt_1+1;end if;k2 <= k1;end if;if key_in = '0' thencnt_1 <= "00"end if;end process;key_out <= not k1 and k2;end Behavioral;4.3.2按鍵消抖電路仿真tb : PROCESSBEGINclk_1k <= '

32、;0' ; wait for 0.5 ms;clk_1k <= '1' ; wait for 0.5 ms;END PROCESS;PROCESSBEGINkey_in <= '1'wait for 10 ms;key_in <= '0'wait for 0.1 ms;key_in <= '1'wait for 0.09 ms;key_in <= '0'wait for 0.1 ms;key_in <= '1'wait for 0.11 ms;key_in

33、 <= '0'wait for 0.12 ms;key_in <= '1'wait for 0.11 ms;key_in <= '0'wait for 0.12 ms;key_in <= '1'wait for 0.1 ms;key_in <= '0'wait for 0.11 ms;key_in <= '1'wait for 0.12 ms;key_in <= '0'wait for 0.1 ms;key_in <= '1&#

34、39;wait for 0.1 ms;key_in <= '0'wait for 10 ms;key_in <= '1'wait for 0.09 ms;key_in <= '0'wait for 0.08 ms;key_in <= '1'wait for 0.1 ms;key_in <= '0'wait for 0.11 ms;key_in <= '1'wait for 0.09 ms;key_in <= '0'wait for 0.1 m

35、s;key_in <= '1'wait for 0.11 ms;key_in <= '0'wait for 0.12 ms;key_in <= '1'wait for 0.1 ms;key_in <= '0'wait for 0.11 ms;key_in <= '1'wait for 0.12 ms;key_in <= '0'wait for 0.1 ms;key_in <= '1'wait for 10 ms;END PROCESS;4.3

36、.3按鍵消抖電路綜合4.4八段譯碼器4.4.1八段譯碼器實現(xiàn)entity baduan is Port ( in_7 : in STD_LOGIC_VECTOR (3 downto 0); seg : out STD_LOGIC_VECTOR (7 downto 0);end baduan;architecture Behavioral of baduan isbeginprocess(in_7)beginCase in_7 iswhen "0000" => seg <="00000011"when "0001" =>

37、; seg <="10011111"when "0010" => seg <="00100101"when "0011" => seg <="00001101"when "0100" => seg <="10011001"when "0101" => seg <="01001001"when "0110" => seg <=&quo

38、t;01000001"when "0111" => seg <="00011111"when "1000" => seg <="00000001"when "1001" => seg <="00001001"when others => seg <="11111101"end case;end process;end Behavioral;4.4.2八段譯碼器仿真tb : PROCESSBEGINi

39、n_7 <= "0000" wait for 1 ms;in_7 <= "0001" wait for 1 ms;in_7 <= "0010" wait for 1 ms;in_7 <= "0011" wait for 1 ms;in_7 <= "0100" wait for 1 ms;in_7 <= "0101" wait for 1 ms;in_7 <= "0110" wait for 1 ms;in_7 &l

40、t;= "0111" wait for 1 ms;in_7 <= "1000" wait for 1 ms;in_7 <= "1001" wait for 1 ms;in_7 <= "1010" wait for 1 ms;in_7 <= "0000" wait for 1 ms;END PROCESS;由圖可見仿真結(jié)果與程序完全符合4.4.3八段譯碼器電路綜合View Technology Schematic ：4.5控制器4.5.1控制器entity kongzhiq

41、i is Port ( clk_1k : in STD_LOGIC; start_stop_out : in STD_LOGIC; split_reset_out : in STD_LOGIC; sreg_out : out STD_LOGIC_VECTOR (2 downto 0);end kongzhiqi;architecture Behavioral of kongzhiqi issignal sreg: STD_LOGIC_VECTOR(2 downto 0):="111"signal snext: STD_LOGIC_VECTOR(2 downto 0);beg

42、inprocess(clk_1k,start_stop_out,split_reset_out)beginif rising_edge(clk_1k) thensreg <= snext;end if;end process;process(start_stop_out,split_reset_out,sreg)begincase sreg iswhen "111" =>if start_stop_out = '1' and split_reset_out = '0' then snext <= "011"

43、;else snext <= sreg;end if; when "011" =>if start_stop_out = '1' and split_reset_out = '0' then snext <= "001"elsif start_stop_out = '0' and split_reset_out = '1' then snext <= "010"else snext <= sreg;end if;when "001&

44、quot; =>if start_stop_out = '0' and split_reset_out = '1' then snext <= "111"elsif start_stop_out = '1' and split_reset_out = '0' then snext <= "011"else snext <= sreg;end if;when "010" =>if start_stop_out = '0' and split_reset_out = '1' then snext <= "011"else snext <= sreg;end if;when others =>snext <= "111"end case;end process;sreg_out <= sreg ;end Behavioral;4.5.1控制器仿真tb : PROCESSBEGINclk_1k <= '0'wait for 0.5 ms;clk_1k <= '1'wait for 0.5 m