實(shí)驗(yàn)三 0-9999計(jì)數(shù)器的設(shè)計(jì)

1、桂林航天工業(yè)學(xué)院學(xué)生實(shí)驗(yàn)報(bào)告課程名稱EDA技術(shù)實(shí)驗(yàn)項(xiàng)目名稱0-9999計(jì)數(shù)器的設(shè)計(jì)開課院（系）及實(shí)驗(yàn)室電子信息與自動(dòng)化學(xué)院實(shí)驗(yàn)日期年月日學(xué)生姓名甘志榮學(xué)號(hào)2013090110212專業(yè)班級(jí)自動(dòng)化2班指導(dǎo)教師龐前娟實(shí)驗(yàn)成績(jī)一、實(shí)驗(yàn)?zāi)康?、掌握VHDL語言的基本結(jié)構(gòu)及編程思想。2、掌握計(jì)數(shù)器的工作原理。3、掌握7段數(shù)碼顯示譯碼器設(shè)計(jì)。4、學(xué)習(xí)VHDL的多層次設(shè)計(jì)方法。二、實(shí)驗(yàn)內(nèi)容1、根據(jù)計(jì)數(shù)器的原理，畫出設(shè)計(jì)電路框圖；2、用VHDL語言編程實(shí)現(xiàn)電路功能；3、下載到開發(fā)板驗(yàn)證；三、實(shí)驗(yàn)結(jié)果1、0-9999計(jì)數(shù)器的頂層設(shè)計(jì)圖如下：2、0-9999計(jì)數(shù)器的低層設(shè)計(jì)（VHDL語言代碼） 分頻器模塊f100

2、的VHDL語言代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity f100 is generic(n1 :integer:=50000000); port(clk:in std_logic; f1:out std_logic);end entity f100;architecture getsec of f100 is -signal secout1 : std_logic :='1' signal cnt1: integer range 0 to n1-1:=0;

3、beginprocess(clk) isbeginif clk'event and clk='1' then cnt1<=cnt1+1; if cnt1<=n1/2 then f1<='0' else f1<='1' end if; if cnt1>=n1-1 then cnt1<=0; end if;end if;end process;end architecture getsec; 計(jì)數(shù)器模塊cout的VHDL語言程序代碼：library ieee;use ieee.std_logic_1164.

4、all;use ieee.std_logic_unsigned.all;entity cout isport(clk:in std_logic; cn1,cn2,cn3,cn4:out std_logic_vector(3 downto 0);end ;architecture c10 of cout is signal temp1,temp2,temp3,temp4:std_logic_vector(3 downto 0); signal g,s,b:std_logic;begin p1:process(clk) begin if( clk'event and clk='1&

5、#39; )then if temp1<"1001"then temp1<=temp1+1;g<='0' else temp1<="0000"g<='1' end if; end if; end process p1; p2:process(g) begin if( g'event and g='1' )then if temp2<"1001"then temp2<=temp2+1;s<='0' else temp2

6、<="0000"s<='1' end if; end if; end process p2; p3:process(s) begin if( s'event and s='1' )then if temp3<"1001"then temp3<=temp3+1;b<='0' else temp3<="0000"b<='1' end if; end if; end process p3; p4:process(b) begin

7、 if( b'event and b='1' )then if temp4<"1001"then temp4<=temp4+1; else temp4<="0000" end if; end if; end process p4; cn1<=temp1;cn2<=temp2;cn3<=temp3;cn4<=temp4;end; 顯示模塊display的VHDL語言的程序代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logi

8、c_unsigned.all;-use ieee.numeric_std.all;-use ieee.std_logic_signed.all;entity display isport(data1,data2,data3,data4:in std_logic_vector(3 downto 0); clk_s:in std_logic; -reset:in std_logic; wei:out std_logic_vector(3 downto 0); duanxuan:out std_logic_vector(7 downto 0);end ;architecture aa of disp

9、lay is signal b:std_logic_vector(1 downto 0); signal temp:std_logic_vector(3 downto 0); signal duan:std_logic_vector(7 downto 0);begin a1:process(clk_s) begin if clk_s'event and clk_s='1' then b<=b+1; end if; end process a1; a2:process(b) begin case b is when "00"=>wei<

10、;="1110" temp<=data1; when "01"=>wei<="1101" temp<=data2; when "10"=>wei<="1011" temp<=data3; when "11"=>wei<="0111" temp<=data4; end case; end process a2; a3:process(temp) begin case temp is when&quo

11、t;0000"=>duan<="11000000" when"0001"=>duan<="11111001" when"0010"=>duan<="10100100" when"0011"=>duan<="10110000" when"0100"=>duan<="10011001" when"0101"=>duan<

12、="10010010" when"0110"=>duan<="10000010" when"0111"=>duan<="11111000" when"1000"=>duan<="10000000" when"1001"=>duan<="10010000" when others=>duan<="11111111" end case; end process a3; duanxuan<=duan;end; 四、實(shí)驗(yàn)結(jié)果分析 本次實(shí)驗(yàn)用了兩個(gè)分頻器，一個(gè)用于計(jì)數(shù)分出1HZ，一個(gè)用于數(shù)碼管的動(dòng)態(tài)顯示分出25000HZ。在計(jì)數(shù)模塊的CLK接入分頻器分出的1HZ,也就是來一個(gè)上升沿