基于DDS信號技術(shù)的信號發(fā)生器的設計

1、 基于DDS信號技術(shù)的信號發(fā)生器的設計直接數(shù)字式頻率合成技術(shù)DDS是新一代的頻率合成技術(shù)，采用數(shù)字控制信號的相位增加技術(shù)，具有頻率分辨率高，頻率切換快，頻率切換時相位連續(xù)和相位噪聲低以及全數(shù)字化易于集成等優(yōu)點而被廣泛采用。一 程序代碼（1） ADDER32Blibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ADDER32B isport(ain : in std_logic_vector(31 downto 0);bin : in std_logic_vector(31 downto

2、0);cout: out std_logic_vector(31 downto 0);end;architecture one of ADDER32B isbegincout <= ain + bin;end;（2）juxing_romLIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY juxing_rom ISPORT(address: IN STD_LOGIC_VECTOR (11 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LO

3、GIC_VECTOR (7 DOWNTO 0);END juxing_rom;ARCHITECTURE SYN OF juxing_rom ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (7 DOWNTO 0);COMPONENT altsyncramGENERIC (address_aclr_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;ou

4、tdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURAL);PORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (11 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END COMPONENT;BEGINq <= sub_wire0(7 DOWNTO 0);altsyncram_component : altsyncramG

5、ENERIC MAP (address_aclr_a => "NONE",init_file => "./MIF/juxing.mif",intended_device_family => "Cyclone",lpm_hint => "ENABLE_RUNTIME_MOD=NO",lpm_type => "altsyncram",numwords_a => 4096,operation_mode => "ROM",outdata_ac

6、lr_a => "NONE",outdata_reg_a => "CLOCK0",widthad_a => 12,width_a => 8,width_byteena_a => 1)PORT MAP (clock0 => clock,address_a => address,q_a => sub_wire0);END SYN;（3）mux3_1library ieee;use ieee.std_logic_1164.all;entity mux3_1 isport( sin:in std_logic_vec

7、tor(7 downto 0); sanjiao,juxing:in std_logic_vector(7 downto 0); a,b:in std_logic; cout:out std_logic_vector(7 downto 0);end mux3_1;architecture behavior of mux3_1 issignal addr:std_logic_vector(1 downto 0);begin process(a,b) begin addr(0)<=a; addr(1)<=b; case addr is when "00" =>

8、 cout<=sin; when "01" => cout<=sanjiao; when "10" => cout<=juxing; when others => null; end case; end process;end behavior;（4）sanjiao_romLIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY sanjiao_rom ISPORT(address: IN STD_LOGIC_

9、VECTOR (11 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END sanjiao_rom;ARCHITECTURE SYN OF sanjiao_rom ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (7 DOWNTO 0);COMPONENT altsyncramGENERIC (address_aclr_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_t

10、ype: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURAL);PORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (11 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END COMPONENT;BEGINq <=

11、 sub_wire0(7 DOWNTO 0);altsyncram_component : altsyncramGENERIC MAP (address_aclr_a => "NONE",init_file => "./MIF/sanjiao.mif",intended_device_family => "Cyclone",lpm_hint => "ENABLE_RUNTIME_MOD=NO",lpm_type => "altsyncram",numwords_a

12、=> 4096,operation_mode => "ROM",outdata_aclr_a => "NONE",outdata_reg_a => "CLOCK0",widthad_a => 12,width_a => 8,width_byteena_a => 1)PORT MAP (clock0 => clock,address_a => address,q_a => sub_wire0);END SYN;（5）sinx256_romLIBRARY ieee;USE iee

13、e.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY sinx256_rom ISPORT(address: IN STD_LOGIC_VECTOR (7 DOWNTO 0);inclock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END sinx256_rom;ARCHITECTURE SYN OF sinx256_rom ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (7 DOWNTO 0);COMPONENT altsync

14、ramGENERIC (address_aclr_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURAL);PORT (clock0: IN STD_LOGIC ;addr

15、ess_a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END COMPONENT;BEGINq <= sub_wire0(7 DOWNTO 0);altsyncram_component : altsyncramGENERIC MAP (address_aclr_a => "NONE",init_file => "./MIF/sinx256_rom.mif",intended_device_family => "Cyc

16、lone",lpm_hint => "ENABLE_RUNTIME_MOD=NO",lpm_type => "altsyncram",numwords_a => 256,operation_mode => "ROM",outdata_aclr_a => "NONE",outdata_reg_a => "CLOCK0",widthad_a => 8,width_a => 8,width_byteena_a => 1)PORT MAP

17、(clock0 => inclock,address_a => address,q_a => sub_wire0);END SYN;（6）REG32Blibrary ieee;use ieee.std_logic_1164.all;entity REG32B isport(clk : in std_logic;din : in std_logic_vector(31 downto 0);dout: out std_logic_vector(31 downto 0);end;architecture one of REG32B isbeginprocess(clk,din)be

18、ginif clk'event and clk = '1' thendout <= din;end if;end process;-dout <= passer ;end;（6）sinLIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY sin ISPORT(address: IN STD_LOGIC_VECTOR (7 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (7 DOWNT

19、O 0);END sin;ARCHITECTURE SYN OF sin ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (7 DOWNTO 0);COMPONENT altsyncramGENERIC (clock_enable_input_a: STRING;clock_enable_output_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURAL);PORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (7 D