計算機(jī)組成原理課設(shè)

1、.計算機(jī)組成原理課程設(shè)計報告題目：設(shè)計一臺嵌入式CISC模型機(jī)院系：計算機(jī)科學(xué)與工程學(xué)院專業(yè)：網(wǎng)絡(luò)工程：麥健豪學(xué)號：1100380215. v.一、課程設(shè)計的題目和內(nèi)容 采用定長CPU周期、聯(lián)合控制方式，并運(yùn)行能完成一定功能的機(jī)器語言源程序進(jìn)展驗(yàn)證，機(jī)器語言源程序功能如下：輸入5個有符號整數(shù)8位二進(jìn)制補(bǔ)碼表示，求最大負(fù)數(shù)的絕對值并輸出顯示。說明：5個有符號數(shù)從外部輸入；一定要使用符號標(biāo)志位比方說SF，并且要使用為負(fù)的時候轉(zhuǎn)移比方JS或不為負(fù)的時候轉(zhuǎn)移比方JNS指令；采用單數(shù)據(jù)總線構(gòu)造的運(yùn)算器。二、系統(tǒng)設(shè)計2.1系統(tǒng)的總體設(shè)計2.2設(shè)計控制器的邏輯構(gòu)造框圖說明：在T4內(nèi)形成微指令的微地址，并訪問

2、控制存儲器，在T2的上邊沿到來時，將讀出的微指令打入微指令存放器，即圖中的微命令存放器和微地址存放器。2.3設(shè)計機(jī)器指令和指令系統(tǒng)指令對象功能機(jī)器指令Mov1XX,RDDATADATA->RD0011TESTXX,RDAC鎖存FS0100JNSXXXXADDRADDR->PC0101INCXX,RDRD+1->RD0110INXX,RDSW->RD0111CMP RS,RDRS-RD鎖存FS1001MOV2RS,RDRS->RD1010JMPXXXXADDRADDR->PC1011NEGXX,RD(0-RD)->RD1100OUTRS,XXRS->

3、;LED1101以下是對Rs,Rd的規(guī)定：Rs或Rd選定的存放器0 0R00 1R11 0R2模型機(jī)規(guī)定數(shù)據(jù)的表示采用定點(diǎn)整數(shù)補(bǔ)碼表示，單字長為8位，其格式如下：76 5 4 3 2 1 0符號位尾數(shù)2.4設(shè)計時序產(chǎn)生器2.5設(shè)計微程序流程圖2.6設(shè)計操作控制器單元(1)設(shè)計微指令格式與微指令代碼表CISC模型機(jī)系統(tǒng)使用的微指令采用全水平型微指令，字長為25位，其中微命令字段為17位，P字段為2位，后繼微地址為6位，其格式如下：設(shè)計的具體指令為：16進(jìn)制微地址LOADLDPCLDARLDIRLDRiRD_BRB_BS1S0ALU_BLDACLDDRWRCSSW_BLED_BLDFRP1P2后繼

4、微地址000000000000001002000010100000000300001100001110040001000000111105000101011000000600011000010010070001110000000009001001000101010A001010000000000B001011000110000C001100000110010D001101000000000E001110000000000F001111000000001201001000000000150101010001011016010110000000001801100000000000190110010

5、000000030110000000000002010000000000000（2） 設(shè)計地址轉(zhuǎn)移邏輯電路地址轉(zhuǎn)移邏輯電路是根據(jù)微程序流程圖的棱形框局部及多個分支微地址，利用微地址存放器的異步置1端，實(shí)現(xiàn)微地址的多路轉(zhuǎn)移的。由于是采用邏輯電路來實(shí)現(xiàn)的，故稱之為地址轉(zhuǎn)移邏輯電路。在微地址流程圖中，P1高電平有效測試時，根據(jù)指令的操作I7I4強(qiáng)制修改后繼地址的低四位；在P2高電平有效時，根據(jù)借位標(biāo)志FS進(jìn)展2路分支，并且都在T4內(nèi)形成后繼微指令的微地址。SE5=(NOT FS) AND P(2) AND T4SE4=(I7 AND P(2) AND T4SE3=(I6 AND P(2) AND T

6、4SE2=(I5 AND P(2) AND T4SE1=(I4 AND P(2) AND T42.7設(shè)計單元頂層電路2.8編寫匯編語言源程序算法：R0存入一個整數(shù)-4，作為五次輸入循環(huán)使用；R1用于存儲輸入的整數(shù)；R3用于存入最后的結(jié)果，并預(yù)存一個最小負(fù)數(shù)-128.隨后如下Mov1 R0,-5將立即數(shù)-4->R0MOV1 R2,-128將立即數(shù)-128 ->R2L1TEST R0測試R0，鎖存SFJNS L2非負(fù)，即SF=0，跳轉(zhuǎn)L2INC R0R0+1IN R1輸入一個整數(shù)，并存入R1TEST R1測試R1JNS L1非負(fù)那么跳轉(zhuǎn)L1CMP R2,R1比擬R2,R1的大小，鎖存S

7、FJNS L1非負(fù)那么跳轉(zhuǎn)L1MOV2 R1,R2將R1的內(nèi)容存入R2JMP L1跳轉(zhuǎn)L1L2NEG R2對R2求補(bǔ)OUT R2輸出結(jié)果2.9 機(jī)器語言源程序指令地址地址16進(jìn)制機(jī)器指令十六進(jìn)制備注Mov1 R0,-500000000000011000030000000010111111011FBMOV1 R2,-12800000010020011001032000000110310000001FFL1TEST R000000100040100000040JNS L20000010105010100005000000110060001001011INC R0000001110701100000

8、60IN R100001000080111000171TEST R100001001090100000141JNS L1000010100A0101000050000010110B0000010004CMP R2,R1000011000C1001100199JNS L1000011010D0101000050000011100E0000010004MOV2 R1,R2000011110F10100110A6JMP L1000100001010110000B000010001110000010004L2NEG R2000100101211000010C2OUT R2000100111311011

9、000D8CISC模型機(jī)的單元電路3.1 ALU單元S1S0功能00AC-DR,鎖存FS01AC 鎖存FS10自加111求補(bǔ)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ALU ISPORT(A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);S1,S0:IN STD_LOGIC;BCDOUT:OUT STD_LOGIC_VECTOR(7 D

10、OWNTO 0);SF:OUT STD_LOGIC);END ALU;ARCHITECTURE A OF ALU ISSIGNAL AA,BB,TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(S1,S0)BEGINIF(S1='0' AND S0='0')THENTEMP<=A-B;SF<=TEMP(7);BCDOUT<=TEMP(7 DOWNTO 0);ELSIF(S1='0' AND S0='1')THENTEMP<=A-0;SF<=TEMP(7);B

11、CDOUT<=TEMP(7 DOWNTO 0);ELSIF(S1='1' AND S0='0')THENTEMP<=A+1;BCDOUT<=TEMP(7 DOWNTO 0);ELSIF(S1='1' AND S0='1')THENTEMP<=0-A;BCDOUT<=TEMP(7 DOWNTO 0);END IF;END PROCESS;END A;3.2存放器單元 LDFR上升沿有效。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LS74 ISPORT

12、(LDFR:IN STD_LOGIC;SF:IN STD_LOGIC;FS:OUT STD_LOGIC);END LS74;ARCHITECTURE A OF LS74 ISBEGINPROCESS(LDFR)BEGINIF(LDFR'EVENT AND LDFR='1')THEN FS<=SF; END IF;END PROCESS;END A;而暫存存放器與通用存放器那么是使用LS273通用存放器功能表RO_1R1_BR2_BALU_B功能1110輸出ALU0111輸出R01011輸出R11101輸出R2LIBRARY IEEE;USE IEEE.STD_LO

13、GIC_1164.ALL;ENTITY LS273 ISPORT( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC; O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END LS273;ARCHITECTURE A OF LS273 ISBEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1') THEN O<=D; END IF; END PROCESS;END A;3.3 1:2分配器單元輸入輸出WRLED_BX7.0W17.0W27.0

14、00XX7.0其他值XX7.0LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY FEN2 ISPORT( X:IN STD_LOGIC_VECTOR(7 DOWNTO 0); WR,LED_B:IN STD_LOGIC; W1,W2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END FEN2;ARCHITECTURE A OF FEN2 ISBEGIN PROCESS(LED_B,WR) BEGIN IF(LED_B='0' AND WR='0') THEN W2<=X; ELSE

15、W1<=X; END IF; END PROCESS;END A;3.4 3選1數(shù)據(jù)選擇器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX3 ISPORT(ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SW_B,CS:IN STD_LOGIC;N1,N2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END MUX3;ARCHITECTURE A OF MUX3 ISBEGIN PROCESS(SW_B,CS) BEG

16、IN IF(SW_B='0') THEN EW<=ID; ELSIF(CS='0')THEN EW<=N2; ELSEEW<=N1;END IF; END PROCESS;END A;3.5 4選1數(shù)據(jù)選擇器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX4 ISPORT(C,D,E,F: IN STD_LOGIC;X1,X2,X3,X4: IN STD_LOGIC_VECTOR(7 DOWNTO 0);W: out STD_LOGIC_VECTOR(7 DOWNTO 0);END MU

17、X4;ARCHITECTURE A OF MUX4 ISSIGNAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN SEL<=F&E&D&C; PROCESS(SEL) BEGIN IF(SEL="1110") THEN -R0_out W<=X1; ELSIF(SEL="1101") THEN -R1_out W<=X2; ELSIF(SEL="1011") THEN -R2-out W<=X3; ELSIF(SEL="0111")

18、 THEN -R3_out W<=X4; ELSE null; END IF; END PROCESS;END A;3.6 程序計數(shù)器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PC ISPORT( load,LDPC,CLR: IN STD_LOGIC; D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); O: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END P

19、C;ARCHITECTURE A OF PC ISSIGNAL QOUT: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(LDPC,CLR,load) BEGIN IF(CLR='0') THEN QOUT<="00000000" ELSIF(LDPC'EVENT AND LDPC='1') THEN IF(load='0') THEN QOUT<=D; -BUS->PC ELSE QOUT<=QOUT+1; -PC+1 END IF; END IF; E

20、ND PROCESS; O<=QOUT;END A;3.7 地址存放器單元同存放器單元3.8主存儲器單元即為ROM。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ROM16 IS PORT(DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0);CS:IN STD_LOGIC);END ROM16;ARCHITECTURE A

21、 OF ROM16 ISBEGINDOUT<="00110000"WHEN ADDR="00000000"AND CS='0'ELSE "11111011"WHEN ADDR="00000001"AND CS='0'ELSE "00110010"WHEN ADDR="00000010"AND CS='0'ELSE "10000001"WHEN ADDR="00000011"AND C

22、S='0'ELSE "01000000"WHEN ADDR="00000100"AND CS='0'ELSE "01010000"WHEN ADDR="00000101"AND CS='0'ELSE "00010010"WHEN ADDR="00000110"AND CS='0'ELSE "01100000"WHEN ADDR="00000111"AND CS='0

23、'ELSE "01110001"WHEN ADDR="00001000"AND CS='0'ELSE "01000001"WHEN ADDR="00001001"AND CS='0'ELSE "01010000"WHEN ADDR="00001010"AND CS='0'ELSE "00000100"WHEN ADDR="00001011"AND CS='0'ELS

24、E "10011001"WHEN ADDR="00001100"AND CS='0'ELSE "01010000"WHEN ADDR="00001101"AND CS='0'ELSE "00000100"WHEN ADDR="00001110"AND CS='0'ELSE "10100110"WHEN ADDR="00001111"AND CS='0'ELSE "

25、10110000"WHEN ADDR="00010000"AND CS='0'ELSE "00000100"WHEN ADDR="00010001"AND CS='0'ELSE "11000010"WHEN ADDR="00010010"AND CS='0'ELSE "11011000"WHEN ADDR="00010011"AND CS='0'ELSE "00000000

26、"END A;3.9 指令存放器單元3.10 時序產(chǎn)生器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNTER ISPORT( Q,CLR: IN STD_LOGIC; T2,T3,T4: OUT STD_LOGIC );END COUNTER;ARCHITECTURE A OF COUNTER ISSIGNAL X: STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN PROCESS(

27、Q,CLR) BEGIN IF(CLR='0') THEN T2<='0' T3<='0' T4<='0' X<="00" ELSIF(Q'EVENT AND Q='1') THENX<=X+1; T2<=(NOT X(1) AND X(0); T3<=X(1) AND (NOT X(0); T4<=X(1) AND X(0); END IF; END PROCESS; END A;3.11 操作控制器單元地址轉(zhuǎn)移邏輯電路ADDRLIBRA

28、RY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDR IS PORT( I7,I6,I5,I4:IN STD_LOGIC; FS,T4,P1,P2:IN STD_LOGIC; SE6,SE5,SE4,SE3,SE2,SE1:OUT STD_LOGIC);END ADDR;ARCHITECTURE A OF ADDR ISBEGINSE6<='1'SE5<=NOT( FS AND P2 AND T4);SE4<=NOT(I7 AND P1 AND T4);SE3<=NOT(I6 AND P1 AND T4);SE2

29、<=NOT(I5 AND P1 AND T4);SE1<=NOT(I4 AND P1 AND T4);END A;微地址存放器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MMM IS PORT( SE:IN STD_LOGIC; T2:IN STD_LOGIC; D:IN STD_LOGIC; CLR:IN STD_LOGIC; UA:OUT STD_LOGIC );END MMM;ARCHITECTURE A OF MMM ISBEGIN PROCESS(CLR,SE,T2) BEGIN IF(CLR='0')

30、THEN UA<='0' ELSIF(SE='0')THEN UA<='1' ELSIF(T2'EVENT AND T2='1') THEN UA<=D; END IF; END PROCESS;END A;微地址轉(zhuǎn)換器F1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F1 ISPORT(UA5,UA4,UA3,UA2,UA1,UA0:IN STD_LOGIC;D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END F1;ARCHIT

31、ECTURE A OF F1 ISBEGIND(5)<=UA5;D(4)<=UA4;D(3)<=UA3;D(2)<=UA2;D(1)<=UA1;D(0)<=UA0;END A;控制存儲器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CONTROM ISPORT(ADDR: IN STD_LOGIC_VECTOR(5 DOWNTO 0); UA:OUT STD_LOGIC_VECTOR(5

32、DOWNTO 0); D:OUT STD_LOGIC_VECTOR(18 DOWNTO 0) );END CONTROM;ARCHITECTURE A OF CONTROM ISSIGNAL DATAOUT: STD_LOGIC_VECTOR(24 DOWNTO 0);BEGIN PROCESS(ADDR) BEGINCASE ADDR ISWHEN "000000"=>DATAOUT<="00000010"WHEN "000010"=>DATAOUT<="10000000"WHEN &qu

33、ot;000011"=>DATAOUT<="00001110"WHEN "000100"=>DATAOUT<="00001111"WHEN "000101"=>DATAOUT<="01100000"WHEN "000110"=>DATAOUT<="00010010"WHEN "000111"=>DATAOUT<="00000000"WHEN &qu

34、ot;001001"=>DATAOUT<="00010101"WHEN "001010"=>DATAOUT<="00000000"-0AWHEN "001011"=>DATAOUT<="00011000"WHEN "001100"=>DATAOUT<="00011001"WHEN "001101"=>DATAOUT<="00000000"WHEN

35、"001110"=>DATAOUT<="00000000"WHEN "001111"=>DATAOUT<="00000000"WHEN "100000"=>DATAOUT<="00000000"WHEN "010010"=>DATAOUT<="00000000"WHEN "010101"=>DATAOUT<="00010110"WHEN

36、"010110"=>DATAOUT<="00000000"-WHEN "010111"=>DATAOUT<="00000000"-17WHEN "011000"=>DATAOUT<="00000000"WHEN "011001"=>DATAOUT<="00000000"WHEN "110000"=>DATAOUT<="00000000"W

37、HEN OTHERS=>DATAOUT<="00000000"END CASE;UA(5 DOWNTO 0)<=DATAOUT(5 DOWNTO 0);D(18 DOWNTO 0)<=DATAOUT(24 DOWNTO 6);END PROCESS;END A;微命令存放器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MMAND ISPORT( T2,T3,T4,I3,I2,I1,

38、I0:IN STD_LOGIC; O:IN STD_LOGIC_VECTOR(18 DOWNTO 0); P1,P2,LOAD,LDPC,LDAR,LDIR,LDR0,LDR1,LDR2,R0_B,R1_B,R2_B,S1,S0,ALU_B,LDAC,LDDR,WR,CS,SW_B,LED_B,LDFR:OUT STD_LOGIC );END MMAND;ARCHITECTURE A OF MMAND ISSIGNAL DATAOUT:STD_LOGIC_VECTOR(18 DOWNTO 0);BEGIN PROCESS(T2) BEGIN IF(T2'EVENT AND T2=

39、9;1')THEN DATAOUT(18 DOWNTO 0)<=O(18 DOWNTO 0); END IF; P2<=DATAOUT(0); P1<=DATAOUT(1); LDFR<=DATAOUT(2) AND T4; LED_B<=DATAOUT(3); SW_B<=DATAOUT(4); CS<=DATAOUT(5); WR<=DATAOUT(6)OR(NOT T3); LDDR<=DATAOUT(7) AND T4; LDAC<=DATAOUT(8) AND T4; ALU_B<=DATAOUT(9); S0

40、<=DATAOUT(10); S1<=DATAOUT(11); R2_B<=(DATAOUT(13)OR(NOT I1)OR I0)AND(DATAOUT(12)OR(NOT I3)OR I2); R1_B<=(DATAOUT(13)OR(NOT I0)OR I1)AND(DATAOUT(12)OR(NOT I2)OR I3); R0_B<=(DATAOUT(13)OR I1 OR I0)AND(DATAOUT(12)OR I3 OR I2); LDR2<=T4 AND DATAOUT(14)AND I1 AND (NOT I0); LDR1<=T4 AND DATAOUT(14)AND (NOT I1) AND I0; LDR0<=T4 AND DATA