Integrated_Circuits(集成電路)電子信息類專業(yè)英語、計(jì)算機(jī)類專業(yè)英語-20頁文檔資料

1、Integrated Circuits(集成電路 )第 19 頁The Integrated CircuitDigitallogic and electronic circuits derive theirfunctionality from electronic switches called transistor. Roughlyspeaking, the transistor can be likened to an electronically controlled valve whereby energy applied to one connection of thevalve e

2、nables energy to flow between two other connections.By combining multiple transistors, digital logic building blocks such as AND gates and flip-flops are formed. Transistors, in turn, aremade from semiconductors. Consult a periodic table of elements ina college chemistry textbook, and you will locat

3、e semiconductorsas a group of elements separating the metals and nonmetals.They are called semiconductors because of their ability to behave as bothmetals and nonmetals. A semiconductor can be made to conduct electricity like a metal or to insulate as a nonmetal does. Thesediffering electrical prope

4、rties can be accurately controlled bymixing the semiconductor with small amounts of other elements. Thismixing is called doping. A semiconductor can be doped to containmore electrons (N-type) or fewer electrons (P-type). Examples ofcommonly used semiconductors are silicon and germanium. Phosphorous

5、and boron are two elements that are used to dope N-type and P-type silicon, respectively.A transistor is constructed by creating a sandwich of differently doped semiconductor layers. The two most common typesof transistors, the bipolar-junction transistor (BJT) and the field-effect transistor (FET)

6、are schematically illustrated in Figure 2.1.This figure shows both the silicon structures of these elements and their graphical symbolic representation as would beseen in a circuit diagram. The BJT shown is an NPN transistor, because it is composed of a sandwich of N-P-N doped silicon. When a small

7、current is injected into the base terminal, a larger current is enabled to flow from the collector to the emitter.The FET shownis an N-channel FET, which is composed of two N-type regions separated by a P-type substrate. When a voltage is applied to theinsulated gate terminal, a current is enabled t

8、o flow from the drain to the source. It is called N-channel, because the gate voltageinduces an N-channel within the substrate, enabling current to flow between the N-regions.Another basic semiconductor structure is a diode, which is formed simply by a junction of N-type and P-type silicon. Diodesac

9、t like one-way valves by conducting current only from P to N.Special diodes can be created that emit light when a voltage isapplied. Appropriately enough, these components are called lightemitting diodes, or LEDs. These small lights are manufactured bythe millions and are found in diverse applicatio

10、ns from telephones to traffic lights.The resulting small chip of semiconductor material on which a transistor or diode is fabricated can be encased in a small plastic package for protection against damage and contamination from the out-side world.Small wires are connected within this package between

11、 the semiconductor sandwich and pins that protrude from the package to makeelectrical contact with other parts of the intended circuit. Once you have several discrete transistors, digital logic can be built by directly wiring these components together. The circuit will function, but any substantial

12、amount of digital logic will be very bulky, because several transistors are required to implement each of the various types of logic gates.At the time of the invention of the transistor in 1947 byJohn Bardeen, Walter Brattain, and William Shockley, the only way to assemble multiple transistors into

13、a single circuit was to buy separate discrete transistors and wire them together. In 1959, Jack Kilby and Robert Noyce independently invented a meansof fabricating multiple transistors on a single slab of semiconductor material.Their invention would come to be known as the integrated circuit, or IC,

14、 which is the foundation of our modern computerized world. An IC is so called because it integrates multiple transistors anddiodes onto the same small semiconductor chip. Instead of havingto solder individual wires between discrete components, an IC contains many small components that are already wi

15、red together in the desired topology to form a circuit.A typical IC, without its plastic or ceramic package, isa square or rectangular silicon die measuring from 2 to 15 mm on an edge. Depending on the level of technology used to manufacture the IC, there may be anywhere from a dozen to tens of mill

16、ions of individual transistors on this small chip. This amazing density of electronic components indicates that the transistors and the wires that connect them are extremely small in size. Dimensions on an IC are measured in units of micrometers, with one micrometer (1mm) being one millionth of a me

17、ter. To serve as a reference point, ahuman hair is roughly 100mm in diameter. Some modern ICs contain components and wires that are measured in increments as small as 0.1mm! Each year, researchers and engineers have been finding new ways to steadily reduce these feature sizes to pack more transistor

18、s into the same silicon area, as indicated in Figure 2.2.When an IC is designed and fabricated, it generally follows one of two main transistor technologies: bipolar or metal-oxide semiconductor (MOS). Bipolar processes create BJTs, whereas MOS processes create FETs. Bipolar logic was more common be

19、fore the1980s, but MOStechnologies have since accounted the great majority of digital logic ICs. N-channel FETs are fabricated in an NMOS process, and P-channel FETs are fabricated in a PMOS process. In the 1980s, complementary-MOS, or CMOS,became the dominant process technology and remains so to th

20、is day. CMOS ICs incorporate both NMOS and PMOS transistors.Application Specific Integrated CircuitAn application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run

21、 a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together for use in many different applications.As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionalit

22、y) possible in an ASIC has grown from 5,000 gates to over 100 million.Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (System-on-Chip). Designers of digital ASICs use a hardware d

23、escription language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.Field-programmable gate arrays (FPGA) are the modern dayequivalent of 7400 series logic and a breadboard, containing programmable logic blocks and programmable interconnects that allow the sameFPGAto be used i

24、n many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design. The non-recurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars.The general term app

25、lication specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs.HistoryThe initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array

26、), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customized by both metal and polysilicon layers. Somebase dies include RAM elements.Standard cell desig

27、nIn the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design tools were available,there was not an effective link from the third party design tools to the layout and actual semiconductor pro

28、cess performance characteristics of the various ASIC manufacturers.Most designers ended up using factory specific tools to complete the implementation of their designs. A solution to this problem that also yielded a muchhigher density device was the implementation of Standard Cells. Every ASIC manuf

29、acturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance; that could also be represented in third party tools.Standard cell design is the utilization of these functional blocks to achieve very high gate density and good elect

30、rical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.By the late 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could compile HDL descriptions into

31、 a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice.These steps, implemented with a level of skill common in the industry, a

32、lmost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from requirements analy

33、sis.*The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (register transfer level) design.*Suitability for purpose is verified by simulation. A virtua

34、lsystem created in software, using a tool such as Virtutech s Simics, can simulate the performance of ASICs at speeds up to billions of simulated instructions per second.*A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large collection of lower-level constructs call

35、ed standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collectionsof gates such as 2 input nor, 2 input nand, inverters, etc.The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cel

36、ls, plus the needed electrical connections between them, is called a gate-level netlist.*The gate-level netlist is next processed by a placementtool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety

37、of specified constraints. Sometimes advancedtechniques such as simulatedannealing are used to optimizeplacement.*The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connectionsbetween them. Since the search space is large, this process wi

38、llproduce a “sufficient” rather than “globally - optimal ” solution.The output is a set of photomasks enabling semiconductor fabrication to produce physical ICs.*Close estimates of final delays, parasitic resistances andcapacitances, and power consumptions can then be made. In the caseof a digital c

39、ircuit, this will be further mapped into delay information. These estimates are used in a final round of testing.This testing demonstrates that the device will function correctlyover all extremes of the process, voltage and temperature. Whenthis testing is complete the photomask information is relea

40、sed for chip fabrication.These design steps (or flow) are also commonto standard product design. The significant difference is that Standard Cell design uses the manufacturer s cell libraries that have been used in hundreds of other design implementations and therefore are of muchlower risk than ful

41、l custom design.Gate array designGate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.The physicaldesign process the

42、n defines the interconnections of the final device. It is important to the designer that minimal propagation delays can be achieved in ASICs versus the FPGA solutions available in the marketplace. Gate array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafe

43、r never gives 100% utilization.Pure, logic-only gate array design is rarely implemented bycircuit designers today, replaced almost entirely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost an

44、d comparable performance.Today gate arrays areevolving into structured ASICs that consist of a large IP core like a processor, DSPunit, peripherals, standard interfaces, integrated memories SRAM,and a block of reconfigurable uncommitted logic.Thisshift is largely because ASIC devices are capable of

45、integrating such large blocks of system functionality and“ system on a chip ”requires far more than just logic blocks.Full-custom designThe benefits of full-custom design usually include reduced area, performance improvements and also the ability to integrate analog components and other pre-designed

46、 components such as microprocessor cores that form a System-on-Chip. The disadvantages can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.However for digi

47、tal only designs,“standard - cell ” libraries together withmodern CADsystems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to manually optimize any performance limiting aspect of the design.Structured d

48、esignStructured ASIC design is an ambiguous expression, with different meanings in different contexts. This is a relatively new term in the industry, which is why there is some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and desi

49、gn cycle time are reducedcompared to cell-based ASIC by virtue of there being pre-defined metal layers and pre-characterization of what is on the silicon.One definition states that, in a structured ASIC design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by

50、a third party). Structured ASIC technology is seen as bridging the gap between field-programmable gate arrays and “standard - cell ” ASIC designs.What makes a structured ASIC different from a gate array is that in a gate array the predefined metal layers serve to make manufacturing turnaround faster

51、. In a structured ASIC the predefined metallization is primarily to reduce cost of the mask sets and is also used to make the design cycle time significantly shorter as well.Likewise, the design tools used for structured ASIC can substantially lower cost, and are easier to use than cell-based tools,

52、 because the tools do not have to perform all the functions that cell-based tools do.One other important aspect about structured ASIC is that it allows IP that is commonto certain applications to be “built in ” , rather than “designed in ” . By building the IP directly into the architecture the desi

53、gner can again save both time and money compared to designing IP into a cell-based ASIC.中文翻譯:集成電路數(shù)字邏輯和電子電路由稱為晶體管的電子開關(guān)得到它們的（各種）功能。粗略地說，晶體管好似一種電子控制閥，由此加在閥一端的能量可以使能量在另外兩個(gè)連接端之間流動(dòng)。通過多個(gè)晶體管的組合就可以構(gòu)成數(shù)字邏輯模塊，如與門和觸發(fā)電路等。而晶體管是由半導(dǎo)體構(gòu)成的。查閱大學(xué)化學(xué)書中的元素周期表，你會(huì)查到半導(dǎo)體是介于金屬與非金屬之間的一類元素。它們之所以被叫做半導(dǎo)體是由于它們表現(xiàn)出來的性質(zhì)類似于金屬和非金屬。可使半導(dǎo)體像金屬

54、那樣導(dǎo)電，或者像非金屬那樣絕緣。通過半導(dǎo)體和少量其它元素的混合可以精確地控制這些不同的電特性，這種混合技術(shù)稱之為“半導(dǎo)體摻雜” 。半導(dǎo)體通過摻雜可以包含更多的電子（ N 型）或更少的電子（ P 型） 。 常用的半導(dǎo)體是硅和鍺， N 型硅半導(dǎo)體摻入磷元素，而 P 型硅半導(dǎo)體摻入硼元素。不同摻雜的半導(dǎo)體層形成的三明治狀?yuàn)A層結(jié)構(gòu)可以構(gòu)成一個(gè)晶體管，最常見的兩類晶體管是雙極型晶體管（BJT）和場效應(yīng)晶體管（FED ,圖2.1 給出了它們的圖示。圖中給出了這些晶體管的硅結(jié)構(gòu)，以及它們用于電路圖中的符號。BJT是NPN晶體管，因?yàn)橛蒒r-P N摻雜硅三層構(gòu)成。當(dāng)小電流注入基極時(shí)，可使較大的電流從集電極流向

55、發(fā)射極。圖示的 FET是 N 溝道的場效應(yīng)型晶體管，它由兩塊被P 型基底分離的 N 型組成。將電壓加在絕緣的柵極上時(shí)，可使電流由漏極流向源極。它被叫做N 溝道是因?yàn)闁艠O電壓誘導(dǎo)基底上的N通道，使電流能在兩個(gè) N區(qū)域之間流動(dòng)。另一個(gè)基本的半導(dǎo)體結(jié)構(gòu)是二極管，由 N 型和 P 型硅連接而成的結(jié)組成。二極管的作用就像一個(gè)單向閥門，由于電流只能從P流向No可以構(gòu)建一些特殊二極管，在加電壓時(shí)可以發(fā)光，這些器件非常合適地被叫做發(fā)光二極管或LEQ這種小燈泡數(shù)以百萬計(jì)地被制造出來，有各種各樣的應(yīng)用，從電話機(jī)到交通燈。半導(dǎo)體材料上制作晶體管或二極管所形成的小芯片用塑料封裝以防損傷和被外界污染。在這封裝里一些短線

56、連接半導(dǎo)體夾層和從封裝內(nèi)伸出的插腳以便與（使用該晶體管的）電路其余部分連接。一旦你有了一些分立的晶體管，直接用電線將這些器件連線在一起就可以構(gòu)建數(shù)字邏輯（電路） 。電路會(huì)工作，但任何實(shí)質(zhì)性的數(shù)字邏輯（電路）都將十分龐大，因?yàn)橐诟鞣N邏輯門中每實(shí)現(xiàn)一種都需要多個(gè)晶體管。1947 年， John Bardeen 、 Walter Brattain 和 and William Shockley發(fā)明晶體管的時(shí)候。將多個(gè)晶體管組裝在一個(gè)電路上的唯一方法就是購買多個(gè)分離的晶體管，將它們連在一起。 1959 年， Jack Kilby 和 RobertNoyce 各自獨(dú)立地發(fā)明了一種將多個(gè)晶體管做在同一片半

57、導(dǎo)體材料上的方法。這個(gè)發(fā)明就是集成電路，或IC ，是我們現(xiàn)代電腦化世界的基礎(chǔ)。集成電路之所以被這樣命名，是因?yàn)樗鼘⒍鄠€(gè)晶體管和二極管集成到同一塊小的半導(dǎo)體芯片上。 IC 包含按照形成電路所要求的拓?fù)浣Y(jié)構(gòu)連在一起的許多小元件，而無需再將分立元件的導(dǎo)線焊接起來。去除了塑料或陶瓷封裝后，一個(gè)典型的集成電路就是每一邊2mm至15mm勺方形或矩形硅片。根據(jù)制造集成電路的技術(shù)水平的不同，在這種小片上可能有幾十個(gè)到幾百萬個(gè)晶體管，電子器件這種令人驚異的密度表明那些晶體管以及連接它們線是極其微小的。集成電路的尺寸是以微米為單位測量的， 1 微米是 1 米的百萬分之一。作為參照，一根人的頭發(fā)其直徑大約為 100

58、 微米。一些現(xiàn)代集成電路包含的元件和連線，是以小到 0.1 微 米的增量來測量的。每年研究人員和工程師都在尋找新的方法來不斷減小這些元件的大小，以便在同樣面積的硅片上集成更多的晶體管，如圖 2.2 所示。在集成電路的設(shè)計(jì)和制造過程中，常用兩種主要晶體管技術(shù)是：雙極和金屬氧化物半導(dǎo)體（MOS。雙極工藝生產(chǎn)出來的是 BJT（雙極型晶體管）， 而MOST藝生產(chǎn)出來的是FET（場效應(yīng)晶體管）。在20世紀(jì)80年代以前更 常用的集成電路是雙極邏輯，但是此后MO茨術(shù)在數(shù)字邏輯集成電路中占據(jù)了大多數(shù)。N溝道FET是采用NMOSC藝生產(chǎn)的，而 P溝道FET是采用 PMOST藝生產(chǎn)白到了 20世紀(jì)80年代，互補(bǔ) MOS1CMO破為占主導(dǎo)地 位的加工技術(shù)，并且延續(xù)至今。CMO集成電路包含了 NMO廊PMOS5種晶 體管。專用集成電路（ ASIC）專用集成電路（ASIC）是為了特殊應(yīng)用而定制的集成電路，而不是通用的。比如，一片僅被設(shè)計(jì)用于運(yùn)行蜂窩式電話的芯片是專用集成電路（ ASIC） 。 相比之下， 7400 與 4000 系列集成電路是可以用導(dǎo)線連接的邏輯構(gòu)建模塊，適用于各種不同的應(yīng)用。隨著逐年