并行IO接口實(shí)驗(yàn).

1、Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaSlide 0Nov, 2015計(jì)算機(jī)計(jì)算機(jī)組成原理與接口組成原理與接口技術(shù)（實(shí)驗(yàn)）技術(shù)（實(shí)驗(yàn)）基于基于MIPS架構(gòu)架構(gòu)實(shí)驗(yàn)4&5 并行IO接口實(shí)驗(yàn)（第1213周）Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technol

2、ogy, Wuhan, Hubei 430074, P.R. ChinaAgenda實(shí)驗(yàn)內(nèi)容目的任務(wù)及時(shí)間安排報(bào)告要求原理回顧Nexys4實(shí)驗(yàn)板簡介Nexys4怎么用？Xilinx的GPIO和INTCGPIO硬件設(shè)計(jì)GPIO應(yīng)用軟件設(shè)計(jì)系統(tǒng)功能測試Slide 1Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China實(shí)驗(yàn)?zāi)康膶?shí)驗(yàn)?zāi)康恼莆誈PIO IP核的工作原理和使用方法掌握中斷控制方式的IO接口設(shè)計(jì)原

3、理掌握中斷程序設(shè)計(jì)方法掌握IO接口程序控制方法查詢方式中斷方式延時(shí)方式Slide 2Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China實(shí)驗(yàn)任務(wù)及時(shí)間安排實(shí)驗(yàn)任務(wù)及時(shí)間安排任務(wù)（第11、13章內(nèi)容）1）按鍵輸入，顯示到console查詢、中斷2）獨(dú)立式開關(guān)輸入，顯示到console查詢、中斷3） Led走馬燈輸出延時(shí)、中斷4）數(shù)碼管滾動(dòng)輸出任意數(shù)字延時(shí)、中斷時(shí)間安排（第1213周）課內(nèi)：兩次課課外：

4、兩周時(shí)間內(nèi)自行添加Slide 3【1】最小硬件系統(tǒng)的建立，按照實(shí)驗(yàn)書第11章內(nèi)容做；【2】參考資料除了實(shí)驗(yàn)書外，請認(rèn)真觀看左老師的實(shí)驗(yàn)視頻。Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China實(shí)驗(yàn)報(bào)告要求實(shí)驗(yàn)報(bào)告要求實(shí)驗(yàn)任務(wù)硬件電路框圖硬件實(shí)現(xiàn)步驟查詢方式、中斷方式、延時(shí)方式軟件流程圖軟件源代碼加注釋心得體會Slide 4Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School

5、of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaAgenda實(shí)驗(yàn)內(nèi)容目的任務(wù)及時(shí)間安排報(bào)告要求原理回顧Nexys4實(shí)驗(yàn)板簡介Nexys4怎么用？Xilinx的GPIO和INTCGPIO硬件設(shè)計(jì)GPIO應(yīng)用軟件設(shè)計(jì)系統(tǒng)功能測試Slide 5Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R.

6、 ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介外觀Slide 6The Nexys4 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7 Field Programmable Gate Array (FPGA) from Xilinx. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external memories, and co

7、llection of USB, Ethernet, and other ports, the Nexys4 can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and a lot of I/O devic

8、es allow the Nexys4 to be used for a wide range of designs without needing any other components. Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介電源供電Slide 71 JP3&J12缺省設(shè)置是按照USB供電2 J6即作為USB供電，也是Jtag調(diào)試接口，還是

9、USB-RS232的接口。Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介FPGA配置Slide 81 JP2&JP1缺省設(shè)置是按照SPI FlashDesigned by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hub

10、ei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介External MemoriesSlide 9The Nexys4 board contains two external memories: a 128Mbit Cellular RAM (pseudo-static DRAM) and a 128Mbit non-volatile serial Flash device. The Cellular RAM has an SRAM interface, and the serial Flash is on a dedicated quad-mode (x4) SPI

11、bus.Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介Ethernet PHYSlide 10The Nexys4 board includes an SMSC 10/100 Ethernet PHY (SMSC part number LAN8720A) paired with an RJ-45 Ethernet jack with integrated ma

12、gnetics. Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介Oscillators/ClocksThe Nexys4 board includes a single 100MHz crystal oscillator connected to pin E3 (E3 is a MRCC input on bank 35).Slide 11Designed by

13、 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介USB-UART Bridge (Serial Port) Slide 12The Nexys4 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that allows you use PC applications to communicate w

14、ith the board using standard Windows COM port commands. Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介VGA Port Slide 13Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Tech

15、nology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介Basis IOButtonSwitchLED7-seg DisResetTri-C LEDs Slide 141 各種IO 會在實(shí)驗(yàn)中頻繁使用，要會看管腳分配。2 本實(shí)驗(yàn)中用到部分3 管腳分配詳見文件：Nexys4_Master.ucfDesigned by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaN

16、exys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介Pmod Connectors Slide 151 提供外部擴(kuò)展能力2 本實(shí)驗(yàn)中可用Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介傳感器溫度加速度 Slide 16Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Tec

17、hnology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介其它鍵盤鼠標(biāo)IICSPI詳見“Nexys4_RM_VB2_Final_5.pdf” Slide 17Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4實(shí)驗(yàn)板簡介實(shí)驗(yàn)板簡介基于Nexys4可以做？簡易數(shù)字示波器簡易數(shù)字信號源VGA貪食蛇小游戲超聲波測距儀簡易手繪畫圖儀簡易電子琴

18、加速度測量儀（跑步計(jì)步器）Slide 18 是考慮賽課結(jié)合題目的時(shí)候了！只有想不到，沒有做不到。Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4怎么用？怎么用？基于Nexys4怎么做？純FPGA方案所有功能用硬件描述語言實(shí)現(xiàn)嵌入式處理器 + 應(yīng)用軟件方案FPGA中設(shè)計(jì)處理器，并運(yùn)行相應(yīng)的 用戶程序，從而實(shí)現(xiàn)相應(yīng)的功能。實(shí)驗(yàn)書第三篇例子都是采用此方案。Slide 19Designed

19、by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4怎么用？怎么用？怎么在Nexys4中建立處理器硬件系統(tǒng)？硬件開發(fā)環(huán)境XPS（Xilinx Platform Studio）BSB建立最小系統(tǒng)（11章）添加基本硬件模塊（13章示例1）每一個(gè)IP核相當(dāng)于一個(gè)集成芯片完成一定功 能，添加IP核之后需要完成各個(gè)IP核之間的 連線以及存儲空間分配（地址譯碼）Slide 20Designed by 楊明，華中科技大

20、學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4怎么用？怎么用？怎么在Nexys4中建立處理器硬件系統(tǒng)？硬件開發(fā)環(huán)境XPS（Xilinx Platform Studio）BSB建立最小系統(tǒng)（11章）添加基本硬件模塊（13章示例1）每一個(gè)IP核相當(dāng)于一個(gè)集成芯片完成一定功 能，添加IP核之后需要完成各個(gè)IP核之間的 連線以及存儲空間分配（地址譯碼）Slide 21Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015

21、.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaNexys4怎么用？怎么用？怎么寫處理器運(yùn)行的用戶程序？軟件開發(fā)環(huán)境SDK（Software Development Kit）C語言具體過程詳見實(shí)驗(yàn)教材第11章以及 第13章示例1Slide 22Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 4

22、30074, P.R. ChinaAgenda實(shí)驗(yàn)內(nèi)容目的任務(wù)及時(shí)間安排報(bào)告要求原理回顧Nexys4實(shí)驗(yàn)板簡介Nexys4怎么用？Xilinx的GPIO和INTCGPIO硬件設(shè)計(jì)GPIO應(yīng)用軟件設(shè)計(jì)系統(tǒng)功能測試Slide 23Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaXilinx的的GPIO和和INTCGPIOGPIO（general purpose IO）是通用并行IO接口的簡稱。它將總

23、線信號轉(zhuǎn)換為IO設(shè)備要求的信號類型，實(shí)現(xiàn)地址譯碼、輸出數(shù)據(jù)鎖存、輸入數(shù)據(jù)緩沖的功能Xilinx AXI總線GPIO IP核包括AXI總線接口模塊、中斷產(chǎn)生邏輯、雙通道I/O模塊每個(gè)通道都可以支持132位的數(shù)據(jù)輸入 輸出，可以配置為單輸入、單輸出或雙 向輸入輸出 怎么配置？ （通過寄存器）Slide 24Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaXilinx的的GPIO和和INTCGPIO內(nèi)

24、部框圖及其寄存器I/O方向當(dāng)GPIO_TRI某位為0時(shí)，GPIO相 應(yīng)的IO引腳配置為輸出；當(dāng)GPIO_TRI某位為1時(shí)，GPIO相 應(yīng)的IO引腳配置為輸入；I/O讀寫Slide 25寄存器名稱偏移地址初始值含義讀寫操作GPIO_DATA0 x00通道1數(shù)據(jù)寄存器通道1數(shù)據(jù)GPIO_TRI0 x40通道1三態(tài)控制寄存器寫控制通道1傳輸方向GPIO2_DATA0 x80通道1數(shù)據(jù)寄存器通道2數(shù)據(jù)GPIO2_TRI0 xC0通道1三態(tài)控制寄存器寫控制通道1傳輸方向# include “xil_io.h”Xil_In8(Addr);Xil_In16(Addr);Xil_In32(Addr);Xil_

25、Out8(Addr, Value);Xil_Out16(Addr, Value);Xil_Out32(Addr, Value);Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaXilinx的的GPIO和和INTCGPIO內(nèi)部框圖及其寄存器I/O模塊的基地址XPS和SDK中均可查看Slide 26寄存器名稱偏移地址初始值含義讀寫操作GPIO_DATA0 x00通道1數(shù)據(jù)寄存器通道1數(shù)據(jù)GPIO_T

26、RI0 x40通道1三態(tài)控制寄存器寫控制通道1傳輸方向GPIO2_DATA0 x80通道1數(shù)據(jù)寄存器通道2數(shù)據(jù)GPIO2_TRI0 xC0通道1三態(tài)控制寄存器寫控制通道1傳輸方向# include “xil_io.h”Xil_In8(Addr);Xil_In16(Addr);Xil_In32(Addr);Xil_Out8(Addr, Value);Xil_Out16(Addr, Value);Xil_Out32(Addr, Value);Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science a

27、nd Technology, Wuhan, Hubei 430074, P.R. ChinaXilinx的的GPIO和和INTCGPIO內(nèi)部框圖及其寄存器I/O中斷Slide 27名稱偏移地址含義讀寫操作GIER0 x11C全局中斷屏蔽寄存器最高位bit31控制GPIO是否輸出中斷信號IrqIP IER0 x128中斷屏蔽寄存器控制各個(gè)通道是否允許產(chǎn)生中斷bit0-通道1；bit1-通道2IP ISR0 x120中斷狀態(tài)寄存器各個(gè)通道的中斷請求狀態(tài)，寫1將清除相應(yīng)位的中斷狀態(tài)bit0-通道1；bit1-通道2Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of E

28、lC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. ChinaXilinx的的GPIO和和INTCAXI INTCSlide 28Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China硬件設(shè)計(jì)硬件設(shè)計(jì)硬件電路框圖MicroBlaze最小系統(tǒng)：第11章GPIO模塊 & AXI INTC：在最小系

29、統(tǒng) 基礎(chǔ)上，用XPS軟件添加(詳見13.5.1節(jié))Slide 29GPIO、AXI 的配置，模塊間的連接等均通過圖形菜單來完成，提高了設(shè)計(jì)效率Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China硬件設(shè)計(jì)硬件設(shè)計(jì)Basis IOButtonSwitchLED7-seg DisResetTri-C LEDs Slide 301 各種IO 會在實(shí)驗(yàn)中頻繁使用，要會看管腳分配。2 本實(shí)驗(yàn)中用到部分3 管腳分

30、配詳見文件：Nexys4_Master.ucfDesigned by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China硬件設(shè)計(jì)硬件設(shè)計(jì)硬件電路初步測試XMD硬件測試：下載完bit流到FPGA之后，就可以采用命令讀取GPIO的寄存器檢驗(yàn)硬件平臺是否工作正常Slide 31因?yàn)閄PS中設(shè)置Dip為Input Only，讀Dip的數(shù)據(jù)寄存器，其值會隨著外接Dip7:0的狀態(tài)而改變。 Dip的輸入/輸出功能正確。寄存器名稱偏移

31、地址初始值含義讀寫操作GPIO_DATA0 x00通道1數(shù)據(jù)寄存器通道1數(shù)據(jù)GPIO_TRI0 x40通道1三態(tài)控制寄存器寫控制通道1傳輸方向GPIO2_DATA0 x80通道1數(shù)據(jù)寄存器通道2數(shù)據(jù)GPIO2_TRI0 xC0通道1三態(tài)控制寄存器寫控制通道1傳輸方向Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China硬件設(shè)計(jì)硬件設(shè)計(jì)硬件電路初步測試XMD硬件測試：下載完bit流到FPGA之后，就可以

32、采用命令讀取GPIO的寄存器檢驗(yàn)硬件平臺是否工作正常Slide 32第1次讀Dip的IP ISR為1，因之前有Dip撥動(dòng)，產(chǎn)生了中斷；寫1到IP ISR會清零IP ISR；有Dip撥動(dòng)后再讀IP ISR又為1；Dip 中斷正確名稱偏移地址含義讀寫操作GIER0 x11C全局中斷屏蔽寄存器最高位bit31控制GPIO是否輸出中斷信號IrqIP IER0 x128中斷屏蔽寄存器控制各個(gè)通道是否允許產(chǎn)生中斷bit0-通道1；bit1-通道2IP ISR0 x120中斷狀態(tài)寄存器各個(gè)通道的中斷請求狀態(tài)，寫1將清除相應(yīng)位的中斷狀態(tài)bit0-通道1；bit1-通道2Dip的IP ISR的地址為0 x400

33、40120Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China硬件設(shè)計(jì)硬件設(shè)計(jì)硬件電路初步測試XMD硬件測試：下載完bit流到FPGA之后，就可以采用命令讀取GPIO的寄存器檢驗(yàn)硬件平臺是否工作正常Slide 33第一次讀Btn IP ISR為0，因?yàn)橹皼]有按下Button；按Button后再讀IP ISR為1；寫1到IP ISR會清零IP ISR。Btn 中斷正確名稱偏移地址含義讀寫操作GIER

34、0 x11C全局中斷屏蔽寄存器最高位bit31控制GPIO是否輸出中斷信號IrqIP IER0 x128中斷屏蔽寄存器控制各個(gè)通道是否允許產(chǎn)生中斷bit0-通道1；bit1-通道2IP ISR0 x120中斷狀態(tài)寄存器各個(gè)通道的中斷請求狀態(tài)，寫1將清除相應(yīng)位的中斷狀態(tài)bit0-通道1；bit1-通道2Button的IP ISR的地址為0 x40000120Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. C

35、hina應(yīng)用軟件設(shè)計(jì)應(yīng)用軟件設(shè)計(jì)使用SDK軟件，設(shè)計(jì)應(yīng)用程序(詳見13.5.1)由MicroBlaze CPU執(zhí)行管理AXI、GPIO模塊，實(shí)現(xiàn)輸 入、中斷等功能函數(shù)接口可以基于已有驅(qū)動(dòng)提供的API也可以直接通過libc提供的輸入輸出 語句對硬件進(jìn)行直接控制Slide 34Designed by 楊明，華中科技大學(xué)電信學(xué)院. 2015.School of ElC, Huazhong University of Science and Technology, Wuhan, Hubei 430074, P.R. China應(yīng)用軟件設(shè)計(jì)應(yīng)用軟件設(shè)計(jì)函數(shù)接口可以基于已有驅(qū)動(dòng)提供的API GPIO位于頭文件xgpio.h中，INTC位于頭文件xintc.h中，CPU位于位于頭文件mb_interface.h中Slide 35實(shí)驗(yàn)書例子采用，需要知道這些函數(shù)的具體含義。程序模塊化程度高。xgpio.h文件中的驅(qū)動(dòng)函數(shù)xintc.h文件中的驅(qū)動(dòng)函數(shù)mb_