實(shí)例教學(xué)七 數(shù)碼管 CPLD FPGA可編程邏輯器件

1、LED數(shù)碼管顯示的VHDL設(shè)計(jì)桂林師范高等?？茖W(xué)校羊日飛LED數(shù)碼管顯示實(shí)例運(yùn)行環(huán)境n紅色颶風(fēng)二代XILINX FPGA開發(fā)板 RC2-3S400 LED數(shù)碼管的板級(jí)硬件電路n四位8段式共陰數(shù)碼管1位2位3位4位位線位線段線段線LED數(shù)碼管的板級(jí)硬件電路nLED數(shù)碼管位線驅(qū)動(dòng)電路qSEG_LED_S0、 SEG_LED_S1、 SEG_LED_S2 SEG_LED_S3 接FPGA相應(yīng)引腳LED數(shù)碼管的板級(jí)硬件電路n8段式共陰數(shù)碼管的段碼一、LED數(shù)碼管的靜態(tài)顯示LED數(shù)碼管的靜態(tài)顯示n四位數(shù)碼管顯示相同的字符n依次顯示從0F的各個(gè)字符，每隔1s顯示一個(gè)字符。 四位數(shù)碼管器件內(nèi)部復(fù)用了每位數(shù)碼

2、管的8條數(shù)據(jù)線（a,b,c,d,e,f,g,dp） 若同時(shí)將四位數(shù)碼管的位線（共陰公共端）接到低電平，則相當(dāng)于同時(shí)選中數(shù)碼管的4個(gè)位。 此時(shí)若段線輸入某個(gè)段碼，則四位數(shù)碼管顯示段碼對(duì)應(yīng)的同一字符。LED數(shù)碼管靜態(tài)顯示的芯片級(jí)設(shè)計(jì)框圖時(shí)鐘源50MHz分頻器計(jì)數(shù)器數(shù)碼管驅(qū)動(dòng)四位LED數(shù)碼管FPGA1/50000000分頻輸出時(shí)鐘信號(hào)的頻率是1Hz，周期為1s。16進(jìn)制計(jì)數(shù)器即有16種狀態(tài)，每經(jīng)過1s計(jì)數(shù)值加“1”，也即跳到下一個(gè)狀態(tài)。段碼譯碼器將16種狀態(tài)碼轉(zhuǎn)換為相應(yīng)的8位二進(jìn)制LED數(shù)碼管段碼段碼。1/50000000分頻器（Divider）entity clkdiv is port( rese

3、t: in std_logic;clkin: in std_logic;clkout: buffer std_logic );end clkdiv;實(shí)體1/50000000分頻器（Divider）architecture clkdiv_stru of clkdiv is signal count: integer range 0 to 25000000:=0;begin process( reset , clkin) begin if reset=0 then count=0; q=0; elsif clkinevent and clkin=1 then if count=25000000 t

4、hen count=0; clkout= not clkout; else count=count+1; end if; end if; end process; end clkdiv_stru;結(jié)構(gòu)體16進(jìn)制計(jì)數(shù)器entity counter is port( reset: in std_logic; clock: in std_logic; countout: out std_logic_vector(3 downto 0) );end counter;architecture counter_stru of counter is signal count: std_logic_vecto

5、r(3 downto 0);begin process( reset , clock) begin if reset=0 then count=“0000”; elsif clockevent and clock=1 then if count=“1111” then count=“0000”; else count=count+ “0001” ; end if; end if; end process; countout Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y , clkin= , clkout=

6、 ); counter_m：counter port map( reset= , clock= ,countout= ); decoderledout_m：decoderledout port map( state= , Y= ); ledbits=“1111”;end led8seg_stru;三個(gè)子模三個(gè)子模塊的元件塊的元件聲明聲明resetmclki_clkreseti_clki_statei_stateledsegsLED數(shù)碼管顯示的VHDL代碼綜合結(jié)果（頂層）LED數(shù)碼管顯示的VHDL代碼綜合結(jié)果（子模塊）二、LED數(shù)碼管的動(dòng)態(tài)顯示LED數(shù)碼管的動(dòng)態(tài)顯示n四位數(shù)碼管顯示不同的字符，比

7、如“1234”n實(shí)現(xiàn)原理：n由于四位數(shù)碼管器件內(nèi)部復(fù)用了每位數(shù)碼管的8條數(shù)據(jù)線（a,b,c,d,e,f,g,dp），所以若要四位數(shù)碼管顯示不同的字符，則一位顯示時(shí)（占用了段線）其它三位應(yīng)該不能顯示。（通過控制位線實(shí)現(xiàn)）LED數(shù)碼管的動(dòng)態(tài)顯示n實(shí)現(xiàn)原理：n由于人眼的視覺暫留效應(yīng)，當(dāng)循環(huán)時(shí)間很短時(shí)，人眼看到的效果如下圖所示：n動(dòng)態(tài)刷新時(shí)間：q電視的場(chǎng)頻：50Hz，即每20ms更新一幅畫面q刷新頻率太慢則會(huì)有閃爍現(xiàn)象q刷新頻率太快則則亮度不夠q一般在幾ms左右作業(yè)：LED數(shù)碼管動(dòng)態(tài)顯示n四位數(shù)碼管顯示不同的字符，比如“1234”修改分頻器architecture clkdiv_stru of clk

8、div is signal count: integer range 0 to 25000000:=0;begin process( reset , clkin) begin if reset=0 then count=0; q=0; elsif clkinevent and clkin=1 then if count=25000000 then count=0; clkout= not clkout; else count=count+1; end if; end if; end process; end clkdiv_stru;結(jié)構(gòu)體architecture clkdiv_stru of

9、clkdiv is signal count: integer range 0 to 50000:=0;begin process( reset , clkin) begin if reset=0 then count=0; q=0; elsif clkinevent and clkin=1 then if count=49999 then count=0; clkout= not clkout; else count=count+1; end if; end if; end process; end clkdiv_stru;修改計(jì)數(shù)器architecture counter_stru of

10、counter is signal count: std_logic_vector(3 downto 0);begin process( reset , clock) begin if reset=0 then count=“0000”; elsif clockevent and clock=1 then if count=“1111” then count=“0000”; else count=count+ “0001” ; end if; end if; end process; countout=count;end counter_stru;architecture counter_st

11、ru of counter is signal count: std_logic_vector(3 downto 0);begin process( reset , clock) begin if reset=0 then count=“0000”; elsif clockevent and clock=1 then if count=“0011” then count=“0000”; else count=count+ “0001” ; end if; end if; end process; countout Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y = “00111111”; ledbits Y = “00000110”; ledbits Y = “