集成電路設(shè)計preface

1、EDA-EIS-Wuhan University1集成電路設(shè)計 Intigrated Circuit Design第一章第一章 集成電路設(shè)計概論集成電路設(shè)計概論EDA-EIS-Wuhan University2n李德識nTEL：68774465,nResearch InterestsqIntelligent System / Embedded SystemqSoC Design & VerificationqAd hoc Networks，Wireless Sensor Networks，Mesh NetworksqSignal Detecting & Processing聯(lián)絡(luò)

2、方式EDA-EIS-Wuhan University3參考書n數(shù)字集成電路數(shù)字集成電路設(shè)計透視（第二版）設(shè)計透視（第二版）Jan MJan M RabaeyRabaey，20042004，清華，清華nDigital Integrated Circuit(A Design Perspective)Digital Integrated Circuit(A Design Perspective)n數(shù)字集成電路數(shù)字集成電路電路、系統(tǒng)與設(shè)計（第二版）電路、系統(tǒng)與設(shè)計（第二版） ，RabaeyRabaey，20042004，電子工業(yè)。電子工業(yè)。n超大規(guī)模集成電路與系統(tǒng)導論，John P. Uyemura，

3、2004，電子工業(yè)。n現(xiàn)代VLSI電路設(shè)計（第二版）（英文），Wolf，2002，科學出版社。n數(shù)字集成電路設(shè)計（英文影印版），Ken Martin ，電子工業(yè)。n專用集成電路Smith，2005，電子工業(yè)。nCMOS數(shù)字集成電路分析與設(shè)計（第三版），Sung-Mo Kang ，電子工業(yè)。EDA-EIS-Wuhan University4關(guān)于Steve JobsnApple founder /CEOn關(guān)鍵詞：iPhone, iPad,ipod,ibook,iMac,Mac OSn領(lǐng)域Pioneer：qPlate Computer Apple，NxETqIntelligent Cell Phon

4、eqDigital Music-iTunesqE-BusinessApp StoreqDigital animated film-Pixar Animation Studio ，Walt DisneyqDigital Textbookn特征：q創(chuàng)新（設(shè)計）、追求完美、控制與堅持能力、良好的商業(yè)模式創(chuàng)新（設(shè)計）、追求完美、控制與堅持能力、良好的商業(yè)模式創(chuàng)新距離并不遙遠，創(chuàng)新造就神奇。創(chuàng)新距離并不遙遠，創(chuàng)新造就神奇。EDA-EIS-Wuhan University5ICs key AdvantagesWhy IC? nSizenSpeednPower ConsumptionnIC to Syste

5、mqSmaller physical sizeqLower power consumptionqReduced costqStable qProtection of Intelligent Property (IP)InnovationEDA-EIS-Wuhan University6課程背景n產(chǎn)業(yè)發(fā)展產(chǎn)業(yè)發(fā)展q七個IC產(chǎn)業(yè)化基地q北京、上海、深圳、西安、杭州、無錫、成都n社會需求社會需求q人才短缺成為瓶頸，建立人才培養(yǎng)基地；n國家扶持國家扶持q軟件及集成電路產(chǎn)業(yè)；n產(chǎn)業(yè)分工的新特點產(chǎn)業(yè)分工的新特點 q知識面要求qFabless (fabrication)，Chipless，Design ho

6、usen知識產(chǎn)權(quán)保護該領(lǐng)域知識和能力帶來的好處n從傳統(tǒng)電子電路到現(xiàn)代技術(shù)從傳統(tǒng)電子電路到現(xiàn)代技術(shù)n電子、信息通信、計算機知識融匯電子、信息通信、計算機知識融匯n源頭創(chuàng)新源頭創(chuàng)新n高質(zhì)量就業(yè)高質(zhì)量就業(yè)n未來創(chuàng)業(yè)基礎(chǔ)未來創(chuàng)業(yè)基礎(chǔ)EDA-EIS-Wuhan University7EDA-EIS-Wuhan University8實驗室建設(shè)&科學研究n實驗室建設(shè)qEDA/FPGAqDSPq嵌入式系統(tǒng)n科學研究qSOCn設(shè)計與驗證方法nCo-Designq互連線qIP CoreqAsicqReconfigurable System,FPGAEDA-EIS-Wuhan University9課程內(nèi)

7、容n集成電路設(shè)計概論集成電路設(shè)計概論q集成電路的發(fā)展， 設(shè)計的要求，設(shè)計方法學，設(shè)計層次，設(shè)計流程。q6hnCMOS集成電路制造技術(shù)集成電路制造技術(shù)Fabricq半導體材料，集成電路制造技術(shù)，CMOS集成電路制造過程。q3hnVerilogHDL建模與仿真建模與仿真-modelingq12hn器件設(shè)計技術(shù)器件設(shè)計技術(shù)-DeviceqMOS晶體管的工作原理，MOS晶體管的直流特性， CMOS反相器直流特性。q6hn電路參數(shù)及性能電路參數(shù)及性能-CircuitqMOS晶體管的參數(shù)，信號傳輸延遲， CMOS電路功耗。q3hn邏輯設(shè)計技術(shù)邏輯設(shè)計技術(shù)Logic designqMOS管的串、并聯(lián)特性，邏

8、輯門的延遲，傳輸門，CMOS邏輯結(jié)構(gòu)，時鐘策略。q6hEDA-EIS-Wuhan University10課程內(nèi)容（續(xù)）n子系統(tǒng)設(shè)計子系統(tǒng)設(shè)計-Subsystemq加法器，寄存器，流水線，存儲器，控制與I/O電路。q12hn版圖設(shè)計技術(shù)版圖設(shè)計技術(shù)-Layoutq版圖設(shè)計過程，版圖設(shè)計規(guī)則。q3hn系統(tǒng)設(shè)計方法與實現(xiàn)技術(shù)系統(tǒng)設(shè)計方法與實現(xiàn)技術(shù)System Designq系統(tǒng)設(shè)計方法，系統(tǒng)實現(xiàn)技術(shù)，門陣列、宏單元陣列及門海，標準單元實現(xiàn)方式，現(xiàn)場可編程門陣列。q3hn可編程邏輯器件設(shè)計技術(shù)可編程邏輯器件設(shè)計技術(shù)Programmable Logic DeviceqFPGA/PLD結(jié)構(gòu)和原理， FP

9、GA/PLD器件編程，F(xiàn)PGA/PLD設(shè)計方法與流程，綜合設(shè)計實例。q12hnSoC設(shè)計設(shè)計System On Chipq設(shè)計經(jīng)濟學，SOC設(shè)計方法，驗證方法。q3hEDA-EIS-Wuhan University11課程名稱及關(guān)系q數(shù)字邏輯；q電子電路設(shè)計；q邏輯設(shè)計與數(shù)字系統(tǒng)；q計算機輔助VLSI設(shè)計；q微電子學概論；qFPGAqEDAEDA-EIS-Wuhan University12課程目標n了解設(shè)計流程；了解設(shè)計流程；n掌握基本概念；掌握基本概念；n理解并掌握集成電路設(shè)計基礎(chǔ)知識；理解并掌握集成電路設(shè)計基礎(chǔ)知識；n設(shè)計數(shù)字電路并進行優(yōu)化；設(shè)計數(shù)字電路并進行優(yōu)化；n配合配合EDA實驗，

10、能夠進行前端設(shè)計；實驗，能夠進行前端設(shè)計；n具備一定的系統(tǒng)設(shè)計能力。具備一定的系統(tǒng)設(shè)計能力。EDA-EIS-Wuhan University13學習方法n課堂q側(cè)重理解側(cè)重理解q做好筆記做好筆記n課后q閱讀閱讀,閱讀，閱讀閱讀，閱讀q查閱參考書q認真完成作業(yè)認真完成作業(yè)-閱讀閱讀paper，Project，習題，習題n配合qEDA實驗q相關(guān)HDL設(shè)計資料q相關(guān)IC設(shè)計案例EDA-EIS-Wuhan University14成績考核n平時成績：大于30%q作業(yè)n任何抄襲行為導致平時成績?yōu)?；n英文表述導致閱讀困難，成績會低于70%；n過度引用，成績會低于70%。q課堂：登記+課堂作業(yè)n考試成績：

11、小于70%EDA-EIS-Wuhan University15EDA實驗使用的環(huán)境及工具n環(huán)境環(huán)境qSUN Solaris，UNIX，LINUXn設(shè)計（設(shè)計（RTL Design）q文本編輯器qWriting Verifiable, Synthesizable VHDL or Verilogn仿真（仿真（Simulation) qVCSqTestbench ，stimulus generation, assertions, output checkingn邏輯綜合（邏輯綜合（Synthesis）q綜合，優(yōu)化n靜態(tài)時序檢查（靜態(tài)時序檢查（Timing Analysis）qPMn形式化驗證（形式化

12、驗證（Formal Verification) qFormalitynFPGAqQuartusIIq實驗系統(tǒng) n電路模擬電路模擬SPICEEDA-EIS-Wuhan University161-1 集成電路發(fā)展EDA-EIS-Wuhan University17信息傳輸?shù)淖冞wEDA-EIS-Wuhan University18The First ComputernCharles Babbage的世界第一臺自動計算器部件差動引擎（Difference Engine，1834)；n25，000 parts；nCost 17,470 Pounds；n基本運算，存放/執(zhí)行，流水線；n元件繼電器(Rel

13、ay)。EDA-EIS-Wuhan University19IBM First Automatic Calculator(Harvard University)EDA-EIS-Wuhan University20ENIAC - The first electronic computer (1946，用于大炮發(fā)射表計算)n賓夕法尼亞大學；n18，000個真空管；n30m*1m*3m,30T,174KW;nElectronic ；nUNIVACI第一臺商用計算機。EDA-EIS-Wuhan University21The Transistor RevolutionFirst transistorB

14、ell Labs, 1947EDA-EIS-Wuhan University22Transistor RevolutionnTransistor Bardeen (Bell Labs) in 1947；q1965,1972諾貝爾物理獎nBipolar transistor Schockley in 1949；nFirst bipolar digital logic gate Harris in 1956；nFirst monolithic IC Jack Kilby（Texas) in 1959；nFirst commercial IC logic gates (TTL) Fairchild

15、1960；nTTL 1962 into the 1990snECL 1974 into the 1980sEDA-EIS-Wuhan University23The First Integrated Circuits Bipolar logic1960sECL 3-input GateMotorola 1966EDA-EIS-Wuhan University24TransistorsnBipolar (PNP, NPN)nFET (Field-Effect)qJFET (Junction)qMOS (Metal-Oxidation Semiconductor)nNMOSnPMOSnCMOSED

16、A-EIS-Wuhan University25MOSFET TechnologynMOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935nCMOS 1960s, but plagued with manufacturing problemsnPMOS in 1960s (calculators)nNMOS in 1970s (4004, 8080) for speednCMOS in 1980s preferred MOSFET technology because of power benefit

17、snBiCMOS, 坤化鎵（Gallium-Arsenide）, 鍺硅（Silicon-Germanium）nCMOS工藝EDA-EIS-Wuhan University261-2 摩爾定律（Moores Law）l1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. lsemiconductor technology will double its effectiveness every 18 months.16151413121110987654321

18、019591960196119621963196419651966196719681969197019711972197319741975LOG2 OF THE NUMBER OFCOMPONENTS PER INTEGRATED FUNCTIONElectronics, April 19, 1965.EDA-EIS-Wuhan University27Transistor Counts1,000,000100,00010,0001,000101001197519801985 19901995 20002005 2010808680286i386i486PentiumPentium ProKP

19、entium IIPentium IIIEDA-EIS-Wuhan University28Moores law in Microprocessors40048008808080858086286386486Pentium procP60.0010.010.1110100100019701980199020002010YearTransistors (MT)2X growth in 1.96 years!Transistors on Lead Microprocessors double every 2 yearsCourtesy, IntelEDA-EIS-Wuhan University2

20、9DRAM Chip Capacity1.6-2.4 m1.0-1.2 m0.7-0.8 m0.5-0.6 m0.35-0.4 m0.18-0.25 m0.13 m0.1 m0.07 mhuman memoryhuman DNAencyclopedia2 hrs CD audio30 sec HDTVbookpage4X growth every 3 years!EDA-EIS-Wuhan University30 Intel 4004 Micro-Processor19712300 transistors1 MHz operation版圖LayoutEDA-EIS-Wuhan Univers

21、ity31Intel Pentium (IV) microprocessor2001； 42 Million；2 GHz clock；電壓更低，功耗更高；模塊化設(shè)計；借助自動化設(shè)計工具。16 Million transistors (Ultra Sparc III)140 Million transistor (HP PA-8500)EDA-EIS-Wuhan University32芯片尺寸/面積（Die Size）40048008808080858086286386486Pentium procP611010019701980199020002010YearDie size (mm2)7%

22、 growth per year2X growth in 10 yearsCourtesy, IntelEDA-EIS-Wuhan University33FrequencyP6Pentium proc486386286808680858080800840040.111010010001000019701980199020002010YearFrequency (Mhz)Lead Microprocessors frequency doubles every 2 yearsDoubles every2 yearsCourtesy, IntelEDA-EIS-Wuhan University34

23、Power will be a major problem5KW 18KW 1.5KW 500W 40048008808080858086286386486Pentium proc0.1110100100010000100000197119741978 198519922000 20042008YearPower (Watts)Courtesy, IntelLead Microprocessors power continues to increaseEDA-EIS-Wuhan University35Power density40048008808080858086286386486Pent

24、ium procP611010010001000019701980199020002010YearPower Density (W/cm2)Hot PlateNuclearReactorRocketNozzlePower density too high to keep junctions at low tempCourtesy, IntelEDA-EIS-Wuhan University36EDA-EIS-Wuhan University37n速度、面積、功耗是IC設(shè)計主要約束條件（多優(yōu)化目標）。EDA-EIS-Wuhan University38Technology Directions:

25、 SIA（美國半導體協(xié)會） RoadmapYear199920022005200820112014Feature size (nm)180130100705035Mtrans/cm2714-2647115284701Chip size (mm2)170170-214235269308354Signal pins/chip76810241024128014081472Clock rate (MHz)6008001100140018002200Wiring levels6-77-88-999-1010Power supply (V)1.81.51.20.90.60.6High-perf power

26、 (W)90130160170174183EDA-EIS-Wuhan University39Source McClean report 2009 BrochureEDA-EIS-Wuhan University40Source: McClean report 2009 BrochureEDA-EIS-Wuhan University41Source: McClean report 2009 BrochureEDA-EIS-Wuhan University42Cell PhoneDigital Cellular MarketAnalog BasebandDigital Baseband(DSP

27、 + MCU)PowerManagementSmall Signal RFPowerRF20102010年中國手機產(chǎn)量增長年中國手機產(chǎn)量增長31%31%，達，達10.1510.15億部，億部，占全球的占全球的 71%,71%,手機出口手機出口7.587.58億部億部 EDA-EIS-Wuhan University43SoC Example: Network ChipEDA-EIS-Wuhan University441-3 IC 分類n按規(guī)模分類：qSSI，少于100門；qMSI，100-1000門；qLSI，1000-10，000門；qVLSI （Very-Large-Scale-Inte

28、grated-Circuits) ，10萬-100萬門；qULSI（Ultra-Large-Scale-Integrated-Circuits)，1000萬門以上。EDA-EIS-Wuhan University45按工藝分類n微米，特征尺寸大于1微米；n亞微米，小于1微米；n深亞微米deep submicron (DSM) ，小于0.6微米；n超深亞微米，小于0.1微米；n典型工藝：q5um, 3um, 2um, 1.2umq1.0um, 0.8um, 0.6um/0.5um, 0.35umq0.25um, q0.07um, . 0.01umEDA-EIS-Wuhan University4

29、6按實現(xiàn)方式分類n全定制ICq積木式基于單元的設(shè)計，基于IP復用的設(shè)計（SOC）。q任意方式。n半定制IC（未制造，根據(jù)功能設(shè)計改變內(nèi)部連線）q門陣列q標準單元n可編程IC（已封裝，可改變引腳及功能）qPLD，CPLDqFPGAEDA-EIS-Wuhan University47按用途分類n通用ICq標準部件，如：譯碼器、多路選通器；q作為商品的存儲器、微處理器。n專用ICqASIC（Application specification Integrated Circuits)q如:衛(wèi)星芯片、GPS芯片、玩具芯片等。EDA-EIS-Wuhan University481-4 產(chǎn)業(yè)（Semicon

30、ductor Related Industry）nDesign (Fabless Company) nCAD Software (EDA) Synopsys, Cadence, MentornManufacturing nMaterial (Wafer, Chemical) nPackaging nTesting Single dieWaferEDA-EIS-Wuhan University49芯片代工廠（chip foundry industry)n臺積電（TSMC），臺灣，58.6億美元（2003）；n聯(lián)電（UMC），臺灣，27.4億美元；n特許半導體（Chartered)，新加坡，7.2

31、5億美元；nIBM，5.55億美元；nNEC，4.25億美元；n中芯國際（SMIC），中國，3.65億美元；n現(xiàn)代，韓國，3.4億美元；IC Insight,2004EDA-EIS-Wuhan University502009 Top20 EDA-EIS-Wuhan University51EDA-EIS-Wuhan University521-5 設(shè)計挑戰(zhàn)（Design Challenges）n微觀問題q速度ultra-high speedsq功耗power dissipation and supply rail dropq互連線延遲interconnectq噪聲、串擾noise, cros

32、stalkq可靠性reliabilityq時鐘分布clock distributionn宏觀問題q上市時間time-to-marketq設(shè)計復雜性design complexity (millions of gates)q抽象層次high levels of abstractionsq設(shè)計重用reuse and IPq片上系統(tǒng)systems on a chip (SoC)q協(xié)同設(shè)計Co-designEDA-EIS-Wuhan University531-6 層次化設(shè)計EDA-EIS-Wuhan University54設(shè)計鴻溝1101001,00010,000100,0001,000,0001

33、0,000,000200319811983198519871989199119931995199719992001200520072009101001,00010,000100,0001,000,00010,000,000100,000,000Logic Tr./ChipTr./Staff Month.xxxxxxx21%/Yr. compoundProductivity growth ratex58%/Yr. compoundedComplexity growth rate10,0001,0001001010.10.010.001Logic Transistor per Chip(M)0.0

34、10.11101001,00010,000100,000Productivity(K) Trans./Staff - Mo.Source: SematechComplexity outpaces design productivityComplexityCourtesy, ITRS RoadmapEDA-EIS-Wuhan University55層次化設(shè)計-動因q工藝特征參數(shù)按 0.7/generation遞減；q芯片功能倍增2x/generation；q功能費用按 2x/generation遞減；q芯片價格無顯著增加；q如何設(shè)計更多functions?q設(shè)計工程師數(shù)量不隨摩爾定律倍增（2年

35、）-n需要更有效的設(shè)計方法q使用不同的抽象層次。EDA-EIS-Wuhan University56抽象抽象(Abstraction)EDA-EIS-Wuhan University57設(shè)計抽象層次（Design Abstraction Levels）Major levels of abstractionq設(shè)計描述( 功能、性能） specification;q結(jié)構(gòu)設(shè)計（模塊） architecture;q邏輯設(shè)計（門、寄存器） logic design;q電路設(shè)計（晶體管，尺寸滿足速度速度、功率需要） circuit design;q版圖設(shè)計（寄生參數(shù)） layout.SYSTEMLOGIC

36、CIRCUITVoutVinCIRCUITVoutVinMODULE+DEVICEn+SDn+GEDA-EIS-Wuhan University58問題n每個層次滿足同樣的設(shè)計要求/約束；n不同層次具有一致性/等價性；n如何評估設(shè)計性能 (gate, block, )?qCost（面積）qReliabilityqSpeed (delay, operating frequency) qPower dissipationEDA-EIS-Wuhan University59Dealing with complexitynVLSI設(shè)計漏斗$ ￥IdeaSand (silicon)CADEngineer

37、MarketSuper ICVLSI設(shè)計漏斗設(shè)計漏斗EDA-EIS-Wuhan University60設(shè)計方法nDivide-and-conquer自頂向下（top-down)的設(shè)計方法nGroup several components into larger components 自低向上(bottom-up)的設(shè)計方法qtransistors gates;qgates functional units;qfunctional units processing elements;qetc.EDA-EIS-Wuhan University61例：Component Hierarchytopi

38、1xxxi2EDA-EIS-Wuhan University62A hierarchical logic designzbox1box2xEDA-EIS-Wuhan University63例:Refinements of electronic design EDA-EIS-Wuhan University64Design abstractionsspecificationbehaviorregister-transferlogiccircuitlayout自然語言ExecutableprogramSequentialmachinesLogic gatestransistorsrectangl

39、esThroughput,design timeFunction units,clock cyclesLiterals, logic depthnanosecondsmicronsTop-downBottom-upEDA-EIS-Wuhan University65例： Layout and its abstractionsnLayout for dynamic latch:EDA-EIS-Wuhan University66棍棒圖Stick diagramEDA-EIS-Wuhan University67Transistor schematicEDA-EIS-Wuhan Universit

40、y68Mixed schematicinverterTransfer gateEDA-EIS-Wuhan University69Circuit abstractionn晶體管尺寸對速度、功耗的影響q表達方式Continuous voltages and time:EDA-EIS-Wuhan University70Digital abstractionn邏輯電平、離散時間discrete time、延遲時間、驅(qū)動能力n布爾方程EDA-EIS-Wuhan University71寄存器傳輸器級（Register-Transfer-Level）抽象n例：Register_X A+Bq只描述系統(tǒng)如

41、何操作，不考慮具體部件(電路）n抽象元件components：運算、存儲n數(shù)據(jù)類型data typesn時鐘周期為單位n狀態(tài)機、數(shù)據(jù)流圖DFG、控制數(shù)據(jù)流圖CDFG+0010000101000111EDA-EIS-Wuhan University721-7 設(shè)計流程n設(shè)計（ Design ）Authoringn版圖（ Layout ） Formattingn制造（ Fabrication ） Printingn封裝（ Packaging ） Bindingn測試（ Testing ）CheckingEDA-EIS-Wuhan University73Design ProcessEDA-EIS-

42、Wuhan University74Typical Design Flow - Industryn產(chǎn)品需求product requirementsn設(shè)計描述design specificationn設(shè)計建模（model/RTL/HDL）n仿真simulation modelqBehavior and/or RTLn功能驗證verificationn邏輯綜合Synthesize to gate level modeln優(yōu)化Logic minimization/ 面向測試的設(shè)計Design for Testn布局布線Place and route/ Physical analysisn制造Fabr

43、icationn測試TestingEDA-EIS-Wuhan University75How to Design an ASICRTLGateTape outMASKFUNCTIONAL SIMULATIONSYNTHESISSTATIC TIMING ANALYSISFLOORPLAN, PLACE/ROUTEPHYSICAL VERIFICATIONTIMING VERIFICATIONVHDLVerilogVITALVerilogGDSIIspecificationDESIGN PLANNINGLogical designLogic Verification“CAE”Fabricatio

44、nPackagingTestingSystem Designentry accumulator is port (DI : in integerDO : inout integer := 0CLK : in bit) ;end accumulator;Physical designPhysical Verification“IC CAD”VITAL（VHDL Initiative Toward ASIC Library） EDA-EIS-Wuhan University76HDL-based Design Flown建立行為模型Create behaviorn測試平臺Consider test

45、abilityn功能仿真Verify/simulate functionalityn綜合Synthesize gate-level Netlistn等效性檢查Compare gate-level and behaviorn靜態(tài)時序分析Verify timingn布局布線Place & routen設(shè)計規(guī)則檢查Verify design rulesn參數(shù)抽取Extract parasiticsEDA-EIS-Wuhan University77設(shè)計說明1.Chip Overview2.Feature List3.Block Diagram4.Function SpecificationE

46、DA-EIS-Wuhan University78設(shè)計規(guī)劃Design Planningn劃分為可綜合模塊； n編寫RTL 代碼；n估計延遲時間。ChipChipSynthesizedCoreMemoryRandom LogicHardCoreAnalogRandom LogicDatapathRFEDA-EIS-Wuhan University79綜合 （Synthesis）n為特定功能，從一個想法（為特定功能，從一個想法（idea）到可制造器件）到可制造器件（manufacturable device）的轉(zhuǎn)換（）的轉(zhuǎn)換（transformation）過程。過程。n自高層次描述到下一層次描述

47、的轉(zhuǎn)換過程。自高層次描述到下一層次描述的轉(zhuǎn)換過程。n系統(tǒng)級綜合系統(tǒng)級綜合算法綜合算法綜合邏輯綜合邏輯綜合物理綜合物理綜合nSynthesis =Translation + Optimization + mappingnRTL Description in VHDL or Verilog HDLEDA-EIS-Wuhan University80Logic Synthesisarchitecture VHDL_1 of VHDL isbegin process begin if CLOCKevent and CLOCK = 1 then if ENABLE = 1 then TOGGLE = not TOGGLE; end if; end if; end process;end VHDL_1;Gate-level Netlist:inv1a U1 (wire3, wire5);dff1 U2 (wire1, wire2, clk);EDA-EIS-Wuhan University81Estimated TimingPlaced ComponentPlaced ComponentNetlist EstimatePhysical EstimateEDA-EIS-Wuhan