教程ni官方培訓(xùn)lesson mimo training system architecture

1、Understand the block diagram of the reference application involved in MIMO system implementation.System FeaturesHardware ComponentsHardware StructureSoftware RequirementsMIMO System Architecture OverviewLesson 2Lesson 2 MIMO System Architecture OverviewA. System FeaturesMIMO Application Framework Fe

2、aturesSystem Design ParametersRadio Frame StructureMIMO Application Framework FeaturesMIMO System Architecture OverviewA. System FeaturesSupported Features Part 1Scalable number of antennas from 4 to 128 at the BS.Data rates and interfaces scale automatically.MU-MIMO detection (1 to 12 MSs).Prototyp

3、ing with 20 MHz bandwidth and LTE like frame structure. Fully reconfigurable frame schedule.Multi-User-MIMO precoding including 12812 ZF, MMSE, and MRC MIMO decoder on FPGA.Bidirectional TDD with fully reconfigurable in uplink and downlink.MIMO Application Framework FeaturesSupported Features Part 2

4、Supports different modulation schemes: QPSK, 16-QAM, 64-QAM, 256-QAM. Aggregates all data to a common central processing unit without bottlenecks.Channel reciprocity calibration per RF channel. Low-latency channel state acquisition, in which the turnaround time is less than the coherence time.Time a

5、nd frequency synchronization over 128 antennas, all using commercial off-the-shelf components. MIMO System Architecture OverviewA. System FeaturesSystem Design ParametersParameterValueNumber of Antennas in BS 4 - 128Number of MSs 1 - 12Baseband Sampling Rate 30.72 MS/sFFT / IFFT order2048Data Subcar

6、riers / Guard Subcarriers (DC)1200 / 848Occupied Channel Bandwidth18.015 MHzModulationOFDMOFDM Symbols per Radio Frame 720 per 10 msCP length160 (for Symbol 0)144 (for Symbols 1-6)MIMO System Architecture OverviewA. System FeaturesRadio Frame Structure: TDD (Example)MIMO System Architecture Overview

7、A. System FeaturesOne Radio frame= 10 ms Frame Schedule is fully reconfigurableSubframe# 0Subframe# 1Subframe# 2Subframe# 3Subframe# 4Subframe# 9UL PilotUL DataUL DataDL PilotDL DataDL DataSwitch GuardOne Subfram1 ms One Slot0.5 ms Sync SignalRadio Frame Structure: TDDThe advantages of using TDD for

8、 MIMO-OFDM systems:Efficient spectrum usageLess complex transceiver designsFlexibility in choosing uplink-to-downlink data-rate ratiosAbility to exploit channel reciprocityAbility to implement in unpaired spectrumMIMO System Architecture OverviewA. System FeaturesLower MAC LayerMAC Header: Comprises

9、 the payload length. Frame Body: Contains information specific to the frame data.Frame Check Sequence (FCS): Contains an IEEE 32-bit cyclic redundancy code (CRC). It is calculated over the MAC Header and the Frame Body field.MIMO System Architecture OverviewA. System Features# bytesPayloadPadding4 b

10、ytesn bytesLSBMSBLSBMSBFCS4 bytesModulationPacket Size in Bytes (header + payload + CRC) QPSK30016-QAM60064-QAM900256-QAM1200Lower MAC Layer: ExampleMIMO System Architecture OverviewA. System FeaturesLesson 2 MIMO System Architecture OverviewB. Hardware ComponentsMIMO System Architecture OverviewB.

11、Hardware Components MIMO Application Framework 1.0RadiosAggregationHost ProcessingFPGA ProcessingTiming and SynchronizationAntennasThe Radio: USRP RIO 294XR / 295XR2 RF Frontends and 1 Kintex-7 FPGA per USRP RIO2x2 MIMO SupportRF band:USRP RIO 2943R : 1.2 GHz to 6 GHzUSRP RIO 2953R : 1.2 GHz to 6 GH

12、z (with GPSDO)x4 MXI Cable with 830 MB/s throughput in each directionMIMO System Architecture OverviewB. Hardware ComponentsMaster Aggregator: PXIe-1085 ChassisIndustrial form factor 18 Slot ChassisGen 2 x8 PCIe backplaneInterconnection of chassis via MXI x8 or x16 cablesMIMO System Architecture Ove

13、rviewB. Hardware ComponentsGen2: 12 GB/s PCI Express Backplane DiagramData Aggregation: CPS-8910 PCIe SwitchboxCombines 8 PCIe connections into a single stream3.2 GB/s data rate through PCIe x8 Gen 2 connectionEnables peer-to peer streaming between USRP RIOsMIMO System Architecture OverviewB. Hardwa

14、re ComponentsThe FPGA Co-processors: FlexRIO 7976RXilinx Kintex-7 K410T FPGA Resources available are64k slices508k flip-flops1540 DSP48 slices2.4 GB/s bidirectional throughput via Gen2 PCIe32 simultaneous high throughput connections to other FPGAsUsed for Data aggregation and Co-processing on FPGAMI

15、MO System Architecture OverviewB. Hardware Componentsx8 PCI Express 2.0 Control of MXI Express:NI PXIe-8384Specificationsthroughput of 3.2 GB/s per directionSoftware-transparent cabled PCI Express link that requires no programming Ability to create multichassis systems using the PXIe-8384 Copper and

16、 Fiber cable options up to 100 mChassis: PXIe-1085MIMO System Architecture OverviewB. Hardware ComponentsTiming and Synchronization Module: NI PXIe-6674TMIMO System Architecture OverviewB. Hardware ComponentsClock and Timing: CDA-2990 (OctoClock) MIMO System Architecture OverviewB. Hardware Componen

17、ts8-channel clock and timing distribution module Amplify & split external 10 MHz reference & PPS (pulse per second) signal 8-ways Matched-length tracesOptional internal GPS Disciplined Version for internal time and frequency referenceEnsures Phase Coherence between USRP RIOs (needed for most MIMO ap

18、plications)Controller: NI PXIe-8135MIMO System Architecture OverviewB. Hardware Components2.3 GHz quad-core Intel Core i7-3610QE processor (3.3 GHz maximum in single-core, Turbo Boost mode)High-bandwidth PXI Express embedded controller with up to 8 GB/s system and 4 GB/s slot bandwidth2 Super Speed

19、USB, 4 Hi-Speed USB, 2 Gigabit Ethernet, GPIB, serial, and other peripheralsWindows OS and drivers already installed; hard drive-based recoveryNote: NI PXIe-8840 and PXIe 8880 are not supported in MIMO Application Framework 1.0Lesson 2 MIMO System Architecture OverviewC. Hardware StructureSystem Blo

20、ck DiagramStandard MIMO ConfigurationsBase Station Hardware ArchitectureSystem Block DiagramMIMO System Architecture OverviewC. Hardware StructureOFDM Modulator and DemodulatorSignal Processing Distribution in the BSSystem Block DiagramMIMO System Architecture OverviewC. Hardware StructureStandard M

21、IMO Configurations: Base StationMIMO System Architecture OverviewC. Hardware Structure8163264128Number of Antennas4Standard MIMO Configurations: Mobile Station1-6 USRP RIOs + Laptops(Emulating 1-12 MSs)MIMO System Architecture OverviewC. Hardware StructureBase Station Hardware Architecture: 16 Anten

22、nasMIMO System Architecture OverviewC. Hardware StructureBase Station Hardware Architecture: 32 AntennasMIMO System Architecture OverviewC. Hardware StructureBase Station Hardware Architecture: 64 AntennasMIMO System Architecture OverviewC. Hardware StructureBase Station Hardware Architecture: 128 A

23、ntennasMIMO System Architecture OverviewC. Hardware StructureLesson 2 MIMO System Architecture OverviewD. Software RequirementsSoftware PrerequisitesHardware NamingSoftware PrerequisitesMicrosoft Windows 8.1 / 7 (64-bit) preinstalled on the PXI controller 8135NI-USRP Driver 15.5LabVIEW Communication System Design Suite 2.0MIMO Application Framework 1.0MIMO System Architecture OverviewD. Software RequirementsHardware NamingDeviceConf.Alia