在系統(tǒng)可編程技術(shù)：第14講 VHDL語言語言時序邏輯電路設(shè)計

1、在系統(tǒng)可編程技術(shù)第14講 VHDL語言語言時序邏輯電路設(shè)計時鐘的描述方法上升沿：CPEVENT AND CP=1下升沿：CPEVENT AND CP=0CP=0CP=0CP=1CP=1CPEVENTCPEVENTCPEVENT上升沿D觸發(fā)器描述方法一：使用信號屬性函數(shù)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS(CP)BEGINIF (CPEVEN

2、T AND CP=1) THENQ=D;END PROCESS;END test;方法二：使用WAIT 語句LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESSBEGINWAIT UNTIL CP=1;Q=D;END PROCESS;END test;上升沿D觸發(fā)器描述方法三：使用上升沿檢測函數(shù)LIBRARY IEEE;USE IEEE.STD_LOGIC

3、_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS(cp)BEGINIF (rising_edge(cp) THENQ=D;END IF;END PROCESS;END test;上升沿D觸發(fā)器描述方法四：使用進程的啟動特性LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);E

4、ND D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS（CP）BEGINIF CP=1 THENQ=D;END IF;END PROCESS;END test;上升沿D觸發(fā)器描述上升沿D觸發(fā)器描述下降沿D觸發(fā)器描述方法一：使用信號屬性函數(shù)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS(CP)BEGINIF

5、 (CPEVENT AND CP=0) THENQ=D;END PROCESS;END test;方法二：使用WAIT 語句LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESSBEGINWAIT UNTIL CP=0;Q=D;END PROCESS;END test;下降沿D觸發(fā)器描述方法三：使用下降沿檢測函數(shù)LIBRARY IEEE;USE IEEE.S

6、TD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS(cp)BEGINIF (falling_edge(cp) THENQ=D;END IF;END PROCESS;END test;下降沿D觸發(fā)器描述方法四：使用進程的啟動特性LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD

7、_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS（CP）BEGINIF CP=0 THENQ=D;END IF;END PROCESS;END test;下降沿D觸發(fā)器描述下降沿D觸發(fā)器描述髙電平D觸發(fā)器描述方法：使用進程的啟動特性LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS（C

8、P，D）BEGINIF CP=1 THENQ=D;END IF;END PROCESS;END test;髙電平D觸發(fā)器描述低電平D觸發(fā)器描述方法：使用進程的啟動特性LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS（CP，D）BEGINIF CP=0 THENQ=D;END IF;END PROCESS;END test;低電平D觸發(fā)器描述LIBRAR

9、Y IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(d,clk,clr:IN STD_LOGIC;q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS (clk, clr) BEGIN IF clr = 1 THEN q = 0; ELSIF clkEVENT AND clk = 1 THEN q = d; END IF;END PROCESS;END test;異步復(fù)位D觸發(fā)器異步復(fù)位D觸發(fā)器ARCHITECTURE test OF D_reg ISB

10、EGINPROCESS (clk) BEGIN IF clkEVENT AND clk = 1 THEN IF clr = 1 THEN q = 0; ELSE q = d; END IF; END IF;END PROCESS;END test;同步復(fù)位D觸發(fā)器同步復(fù)位D觸發(fā)器例：設(shè)計一異步清零、同步置數(shù)的同步8421BCD碼計數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT10 IS PORT(CLK,R,S:IN STD_LOGIC;DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);CO:OUT STD_LOGIC;Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END COUNT10;時序電路設(shè)計舉例ARCHITECTURE test OF COUNT10 ISBEGINCO=1 WHEN (Q=1001) ELSE 0;PROCESS(CLK