數(shù)字邏輯設(shè)計(jì)及應(yīng)用教學(xué)課件：8-3 時(shí)序電路的設(shè)計(jì)移位計(jì)數(shù)器

1、 CLKCLRLDENPENTA QAB QBC QCD QD RCO74x16301+5VCLOCKWhat is the modulo of the circuit below?Answer Key CLKCLRLDENPENTA QAB QBC QCD QD RCO74x16301+5VCLOCKD LD-L CQD QC QB QA0 0 0 00 0 1 00 1 1 00 1 1 11 0 0 01 0 1 01 1 1 01 1 1 1Review of last classan MSI 4-bit bidirectional, parallel-in, parallel-out

2、 shift register (4位雙向移位寄存器74x194) CLKCLRS1S0LIND QDC QCB QBA QARIN74x194left-in 左移輸入right-in 右移輸入left means “in the direction from QD to QA,” right means “in the direction from QA to QD.”Function table for the74x194 4-bit universalshift register CLKCLRS1S0LIND QDC QCB QBA QARIN74x194 CLKCLRS1S0LIND

3、QDC QCB QBA QARINCLKCLRS1S0LINRIN移位寄存器的擴(kuò)展并行輸入（8位）并行輸出8位8.5.3 Shift-Register CountersSerial/parallel conversion is a “data” application, but shift registers have “nondata” applications as well. A shift register can be combined with combinational logic to form a state machine whose state diagram is cy

4、clic. Such a circuit is called a shift-register counter. Unlike a binary counter, a shift-register counter does not count in an ascending or descending binary sequence, but it is useful in many “control” applications.8.5.5 Shift-Register Counters(移位寄存器計(jì)數(shù)器)D0 = F ( Q0 , Q1 , , Qn-1 )Feedback logicD Q

5、 CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3一般結(jié)構(gòu)： 1000010000010010有效狀態(tài)其他狀態(tài)8.5.6 Ring Counters (環(huán)型計(jì)數(shù)器)D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF31000010000010010D0 D1 D2 D3 非自啟動(dòng)的無效狀態(tài)D0 = Qn-1self-correcting counter self-correcting counter is designed so that all abnormal states have transitions l

6、eading to normal states. Self-correcting counters are desirable for the same reason that we use a minimal-risk approach to state assignment : If something unexpected happens, a counter or state machine should go to a “safe” state. 1000010000010010有效狀態(tài)其他狀態(tài)8.5.6 Ring Counters (環(huán)型計(jì)數(shù)器)1000010000010010 非

7、自啟動(dòng)的無效狀態(tài)D0 = Qn-1有效狀態(tài)無效狀態(tài)D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF31000010000010010D0 D1 D2 D3self-correcting自啟動(dòng)的,自校正的Johnson Counter（扭環(huán)計(jì)數(shù)器）D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3D0 = Qn-100001000110011101111011100110001無效有效的狀態(tài)循環(huán)Shift-Register Counters一般結(jié)構(gòu)：反 饋 邏 輯D0 = F ( Q0 , Q1 , , Qn

8、-1 )環(huán)形計(jì)數(shù)器：1000010000100001最簡(jiǎn)單的：D0 = Qn-1反 饋 邏 輯自校正的：D0 = (Qn-2 + + Q1 + Q0)0111101111011110(Qn-2 Q1 Q0) D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3Q3Q0Q2Q1Q0 Q1 Q2 Q3RING COUNTER(P735)The major appeal of a ring counter for control applications is that its states appear in 1-out-of-n decoded form

9、 directly on the flip-flop outputs. That is,exactly one flip-flop output is asserted in each state. Furthermore, these outputs are “glitch free”. For the general case, an n-bit self-correcting ring counter uses an n-1-input NOR gate, and corrects an abnormal state within n - 1 clock ticks.JOHNSON CO

10、UNTER：最簡(jiǎn)單的實(shí)現(xiàn)：D0 = Qn-1D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF31001010010101101011010110101001000001000110011101111011100110001有效狀態(tài)無效狀態(tài)如何得到自校正的扭環(huán)計(jì)數(shù)器？Q3Q0Q2Q1Q0 Q1 Q2 Q3Johnson counter(P533)An n-bit shift register with the complement of the serial output fed back into the serial input is a coun

11、ter with 2n states and is called a twisted-ring, Moebius, orJohnson counter.An n-bit Johnson counter has 2n - 2n abnormal states, and is therefore subject to the same robustness problems as a ring counter. Johnson counterdddddddd最小成本self-correcting1、確定有效的狀態(tài)循環(huán)2、對(duì)無效狀態(tài)進(jìn)行處理， 使其進(jìn)入有效循環(huán)。Q0 Q1 Q2 Q311110000

12、11110000Q0Q100 01 11 1000011110Q2Q3D0100001000110011101111011100110001有效無效100101001010110101101011010100101D0 = Q3 + Q2Q1= ( (Q2Q1) Q3)D0 = Q3 + Q2Q1Self-correcting 4-bit,8-state Johnson counterSelf-correcting 4-bit,4 state ring counter with a single circulating 1Q0Q1Q2Q310CLOCKQ0Q1Q2Q3101000Q0Q1Q2Q

13、3RESET載入Q0Q1Q2Q3CLOCK自校正的Self-correcting 4-bit,8 state Johnson counter CLKCLRS1S0LIND QDC QCB QBA QARIN74x194+5VCLOCKRESET_LS1S0 wired as a shift-left shift register(接成左移形式)自校正改進(jìn)：（法一）LIN = Q3 + Q2Q1Q0Q1Q2Q3self-correcting1、確定有效的狀態(tài)循環(huán)2、對(duì)無效狀態(tài)進(jìn)行處理， 使其進(jìn)入有效循環(huán)。Q0 Q1 Q2 Q300001000110011101111011100110001有效無

14、效10010100101011010110101101010010可利用置數(shù)法。自校正改進(jìn)：每當(dāng)電路Q3Q2Q1Q0出現(xiàn)0XX0就置數(shù)到下一狀態(tài)0001D0 = Q3.Q0Self-correcting 4-bit,8 state Johnson counter CLKCLRS1S0LIND QDC QCB QBA QARIN74x194+5VCLOCKRESET_L自校正改進(jìn)：（法二）利用置數(shù)每當(dāng)電路Q3Q2Q1Q0出現(xiàn)0XX0就置數(shù)到下一狀態(tài)0001,S0 = Q3.Q0Q0Q1Q2Q300018.5.6 Linear Feedback Shift Register Counters線性反

15、饋移位寄存器（LFSR）計(jì)數(shù)器LFSR計(jì)數(shù)器 有 2n-1 種有效狀態(tài) 最大長(zhǎng)度序列發(fā)生器反 饋 邏 輯D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3移位寄存器型計(jì)數(shù)器的一般結(jié)構(gòu)RESET_LCLOCKLFSR n -bit Linear Feedback Shift Register Counters a maximum-length sequence generator. 奇校驗(yàn)電路全0態(tài)的下一狀態(tài)？反饋方程 P535 表8-21LFSR計(jì)數(shù)器 有 2n-1 種有效狀態(tài) 最大長(zhǎng)度序列發(fā)生器偽隨機(jī)序列發(fā)生器EN猜謎游戲機(jī)L1L4ERRG1G4C

16、LOCK使能輸入隨機(jī)產(chǎn)生典型應(yīng)用：產(chǎn)生邏輯電路的測(cè)試輸入信號(hào) 用于檢錯(cuò)及糾錯(cuò)碼的編碼和譯碼電路LFSR計(jì)數(shù)器順序脈沖發(fā)生器利用移位寄存器構(gòu)成 注意自校正（環(huán)形計(jì)數(shù)器 ）利用計(jì)數(shù)器和譯碼器構(gòu)成 注意“毛刺”（二進(jìn)制計(jì)數(shù)器的狀態(tài)譯碼 ）CLKQ0Q1Q2Q3序列信號(hào)發(fā)生器 用于產(chǎn)生一組特定的串行數(shù)字信號(hào)例：設(shè)計(jì)一個(gè) 110100 序列信號(hào)發(fā)生器利用觸發(fā)器利用計(jì)數(shù)器利用移位寄存器利用D觸發(fā)器設(shè)計(jì)一個(gè)110100序列信號(hào)發(fā)生器1、畫狀態(tài)轉(zhuǎn)換圖2、狀態(tài)編碼000101 表示 S0 S5S0S1S5S2S4S3/1/1/0/1/0/03、列狀態(tài)轉(zhuǎn)換輸出表0 0 00 0 10 1 00 1 11 0 01

17、 0 10 0 10 1 00 1 11 0 01 0 10 0 0Q2Q1Q0Q2*Q1*Q0*Y1101004、得到激勵(lì)方程和輸出方程 考慮未用狀態(tài)的處理5、得到電路圖000001用計(jì)數(shù)器和數(shù)據(jù)選擇器構(gòu)成序列信號(hào)發(fā)生器74x163 CLKCLRLDENPENTA QAB QBC QCD QD RCOENABCD0D1D2D3D4D5D6D7YY74x151例：產(chǎn)生一個(gè)8位的序列信號(hào) 00010111+5V+5V序列信號(hào)輸出用移位寄存器構(gòu)成序列信號(hào)發(fā)生器例：產(chǎn)生一個(gè)8位的序列信號(hào) 0001011110111000Q2Q1Q00 0 00 0 10 1 01 0 10 1 11 1 11 1 01 0 0D0Q2Q1Q00100011110LIN01101001LIN = Q2Q1Q0 + Q2Q1 + Q2Q0 CLKCLRS1S0LIND QDC QCB QBA QARIN74x194+5VCLOCKRESET_LQ0Q1Q2Q