數(shù)字邏輯設(shè)計及應(yīng)用教學英文課件：Lec22 chap 08 shift rigister

1、1Digital Logic Design and ApplicationLecture #22Shift RegisterUESTC, Spring 20132Last TimeMSI Counters74x161, 74x163: 4-bit binary up counter74x160, 74x162: decade counter (BCD)74x169: 4-bit binary up/down counterNotice: the difference between synchronous clear/load and asynchronous clear/loadThe co

2、unters can be used as frequency divider.3Last TimeDesign a modulo-m counter using n-bit binary counterConsider two cases: m 2nS0S1S2S3S4S12S11S10S9S8S7S6S5S13S14S15Clear, LoadCascading注意：清零法需要額外設(shè)計進位輸出端，置數(shù)法不需要48.5 Shift RegisterShifting its stored data by one bit position at each clock tickFor handli

3、ng serial data, such as RS-232 and modem transmission and reception, Ethernet links, SONET, etc.Shift-Register StructureMSI Shift RegisterShift-Register Application51. Shift-Register StructureSISO(串入串出) shift-registerCLK01234 Q3 Q2 Q1 Q00 0 0 00 0 0 A0 0 A B0 A B CA B C DserinABCDX serinseroutQ3Q2Q1

4、Q0serout0000A After 4 clks all the serial inputs are shifted in D FFAfter another extra 3 clks all the serial inputs are shifted out of D FF1. Shift-Register StructureSIPO(串入并出)shift-register6serial-in, parallel-outserial-to-parallel conversionAfter 4 clks all the serial inputs are shifted in D FFAt

5、 the 4th clk all the inputs are read out simultaneously by a read pulse&readA modulo-4 counter can be used to generate the read out pulse7Parallel-inserial-outParallel-to-serial conversionLOAD / SHIFTSERINSEROUTCLOCK1D2DNDMUXloadloadloadshiftshiftshift8LOAD / SHIFTSERINNQCLOCK1D2DND1Q2QParallel-inpa

6、rallel-outDo both, serial/parallel conversion92. MSI Shift Register4-bit universal shift register 74x194 CLKCLRS1S0LIND QDC QCB QBA QARINS1 S0 function0 0 hold 0 1 shift right1 0 shift left1 1 loadShift leftShift rightP730 table 8-24 Shift right：RIN QA QB QCShift left：QB QC QD LIN QA* QB* QC* QD*Bi-

7、directional 10One stage of 74x19400S1S0hold S1 S0S1 S010Shift left01Shift right11load P731 Figure8-41 Qi* = S1S0Qi + S1S0Qi-1 + S1S0Qi+1 + S1S0INi QDQBQBQAQD11 CLKCLRS1S0LIND QDC QCB QBA QARIN74x194 CLKCLRS1S0LIND QDC QCB QBA QARINCLKCLRLINRINParallel-in8-bit parallelout 8-bit cascadingQH.QB QAH.B A

8、100 1 Expansion of 74x19412design a 3-bit shift register use 194.Serial inputSerial output CLKCLRS1S0LINRINABCDQDQCQBQASerial inputSerial output133. Shift-Register CountersShift-Register Applicationserial/parallel conversionshift-register countersequential pulse generatorsequence generator/detector

9、ring countertwisted ring counterlinear feedback counter14 Shift-Register Counters structureD0 = F ( Q0 , Q1 , , Qn-1 ) Feedback LogicD Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3利用反饋邏輯可以實現(xiàn) 模2模16 的計數(shù)器 可實現(xiàn)包含202n個狀態(tài)的循環(huán)。Serial input151000010000010010normal statesother states4. Ring counterD Q CK QD Q

10、CK QD Q CK QD Q CK QCLKFF0FF1FF2FF31000010000010010It is not robust.invalid statesD0 = Qn-1Q0Q1Q2Q3Q0Q1Q2Q3Shift rightShift rightShift left16Q0Q1Q2Q3normal states1000010000010010It is not robust.invalid statesD Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3self-correctingsequential pulse generator17u

11、sing 74x194 as ring counterQ0Q1Q2Q310CLOCKQ0Q1Q2Q3101000Q0Q1Q2Q3RESET(Load)Q0Q1Q2Q3CLOCK self-correcting真正的自校正設(shè)計不需要專門的RESET信號 185. Johnson CounterD Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3D0 = Qn-100001000110011101111011100110001invalidnormal cycletwisted ring counterHow to get a self-correctin

12、g design?19Self-correcting design (1)dddddddd最小成本 1、確定有效的狀態(tài)循環(huán) 2、對無效狀態(tài)進行處理， 使其進入有效循環(huán)。Q0 Q1 Q2 Q31111000011110000Q0Q100 01 11 1000011110Q2Q3100001000110011101111011100110001有效無效100101001010110101101011010100101D0 = Q3 + Q2Q1= ( (Q2Q1) Q3) 最小風險：在不改變移位特性的基礎(chǔ)上，對未用狀態(tài)的次態(tài)進行設(shè)計。D0= Qn-1D020 CLKCLRS1S0LIND QDC

13、QCB QBA QARIN74x194+5VCLOCKRESET_LS1S0接成左移形式 自校 正改進：（法一）D0 = Q3 + Q2Q1 Q0Q1Q2Q3Using 74x194 as a Johnson counter21Self-correcting design (2)00001000110011101111011100110001有效無效10010100101011010110101101010010自校正改進：（法二）利用置數(shù)每當電路出現(xiàn) 0XX0 下一狀態(tài)就是 1000 Q0Q1Q2Q3 Q0 Q1 Q2 Q3注意：教材P736上的狀態(tài)順序為Q3Q2Q1Q0 每當電路出現(xiàn) 1X

14、X1 下一狀態(tài)就是 0111 Q0Q1Q2Q3 22Using 74x194 as a Johnson counter+5V CLKCLRS1S0LIND QDC QCB QBA QARIN74x194CLOCKRESET_LQ0Q1Q2Q3自校正改進：（法二）利用置數(shù)每當電路出現(xiàn) 0XX0 下一狀態(tài)就是 1000 Q0Q1Q2Q3 S0 = Q3Q01000236. Linear Feedback Shift-Register CountersPseudo-random number generatorhave 2n1 states, maximum-length sequence gene

15、ratorRESET_LCLOCKodd-parity circuit 全0態(tài)的下一狀態(tài)？ 24257. Shift-Register Applicationserial/parallel conversionshift-register countersequential pulse generatorsequence detectorSequence generator267.1 Sequential Pulse GeneratorUsing shift-register notice: self-correcting ( ring counter )Using binary counte

16、r and decoder notice: “glitch” ( Decoding Binary-Counter States )CLKQ0Q1Q2Q31-out-of-m277.2 Sequence Detector設(shè)計一個110串行序列檢測電路， 利用移位寄存器實現(xiàn) CLKCLRS1S0LIND QDC QCB QBA QARIN74x194+5VCLOCKRESET_LAZ當電路檢測到 輸入A 連續(xù)出現(xiàn)110 時，輸出Z為1輸入A 連續(xù)出現(xiàn)110， 且輸入B為1 時，輸出Z為1。1、待檢測序列長度為3，所以選擇3位 移位寄存器；2、選用通用移位寄存器的串行輸入3、將待檢測序列從狀態(tài)輸出中

17、解讀出來；（組合邏輯）Last timeShift register structureSISO, PISO, SIPO, PIPO74x194 ring counterN-bit m-N counterTwisted ring counterN-bit m-2N counterlinear feedback counterN-bit m-2n-1Shift register counter applications28Self-correcting design feed back function Load297.3 serial signal generator to generate

18、a set of serial digital signalDesign a serial signal generator with the following sequence: 110100Using flip-flops chapter 7Using counterUsing shift register30Using D Flip-Flops to generate 110100 sequence1. State Diagram 2. State assignment000101 表示 S0 S5 S0S1S5S2S4S3/1/1/0/1/0/03. Transition/outpu

19、t Table0 0 00 0 10 1 00 1 11 0 01 0 10 0 10 1 00 1 11 0 01 0 10 0 0Q2Q1Q0Q2*Q1*Q0*Y1101004. Excitation/output Equation consider the unused state5. Circuit diagram計數(shù)器00000131sequence generator using counter + multiplexer74x163 CLKCLRLDENPENTA QAB QBC QCD QD RCOENABCD0D1D2D3D4D5D6D7YY74x151Example: ge

20、nerate a 8-bit sequence 00010111+5V+5V序列 信號 輸出 思考：使用輸出端Y時，Di怎么接？32sequence generator using shift register （counter）Q2Q1Q00 0 00 0 10 1 01 0 10 1 11 1 11 1 01 0 0D0Shift leftQ2Q1Q00100011110D001101001D = Q2Q1Q0 + Q2Q1 + Q2Q0Example: generate a 8-bit sequence 00010111N位移位寄存器計數(shù)器的狀態(tài)循環(huán)中包含的最大狀態(tài)數(shù)為2n. 每個狀態(tài)對

21、應(yīng)一位串行輸出，則N位移位寄存器計數(shù)器可循環(huán)產(chǎn)生的序列最大長度為2n .對一個長度為m的序列，采用移位寄存器來產(chǎn)生，所需寄存器的個數(shù)（位數(shù)）至少為nlog2m.0 0 0 1 0 1 1 1 1 0 1 1 1 0 0 033sequence generator using shift register （counter） CLKCLRS1S0LIND QDC QCB QBA QARIN74x194+5VCLOCKRESET_LQ0Q1Q2 組合邏輯 Example1 : generate a 8-bit sequence 0001011110111000Q2Q1Q00 0 00 0 10 1 01 0 10 1 11 1 11 1 01 0 0D0LIN=D0 = Q2Q1Q0 + Q2Q1 + Q2Q0sequence generator using shift register （counter）34Ex2：design a “101110” sequence generator；（minimum cost） 通過移位特性構(gòu)建狀態(tài)圖（假設(shè)左移；要求狀態(tài)圖中不能出現(xiàn)重復(fù)狀態(tài)）；如果選則三位：101011111110101010如果選則四位Q3Q2Q1Q0：10