講義案例講稿1

1、EL6453 On Chip Debug On Chip Debug 2013 Polytechnic Institute of New York UniversityWhy on chip debug?FPGA designs are ing more complexDesigns are ing fasterDesign times are ing shorterDebugging and verification are more challengingDebugging and verification consume a significant portion of FPGA des

2、ign timeDebugging and verification need to be easier and integrated into the FPGA design flowOn chip Debug This technique provides the designers with the ability to debug their design in the target system, at target speed, at the VHDL RTL level.The VHDL for the device is read into a tool that automa

3、tically creates and inserts a small debug core into the device that probes internal signals. The debug core is created based on information from the designer about what signals are to be probed. The debug core communicates through the JTAG port on the device to an HDL debugger executing on a host pl

4、atform. The HDL debugger sends and receives data from the debug core and displays this data in context with an HDL for the design. Waveforms of the internal device can also be displayed, providing the ability to trace down problems in the design.Real World High Level Design FlowOn-Chip Debug - When

5、to useUse the On-Chip Debug software forVerification and debugInjecting short signal sequencesDo not use the On-Chip Debug software forA replacement for functional and/or timing simulations.Xilinx Chipscope CoresICON (Integrated Control) coreThis core controls up to 15 capture coresThe ICON core int

6、erfaces between the JTAG interface and the capture coresILA (Integrated Logic Analyzer) coreCapture core for HDL designsThe ILA core is a customizable logic analyzer core that can be used to monitor any internal signal of your design.Customizable number, width, and storage of trigger ports VIO (Virt

7、ual Input/Output) core Define and generate virtual I/O portsILA Core - FeaturesILA Core Features:Wide Trigger PortsEach trigger port can be up to 256 bits wideMultiple Trigger PortsEach ILA can have up to 16 trigger portsMultiple Match Units per Trigger PortEach trigger port can be connected up to 1

8、6 match units. Enables multiple comparisons to be performed on the trigger port signals.Boolean Equation Trigger ConditionMulti-Level Trigger SequencerChoice of Match Unit TypesChoice of Match Function Event CounterNote: Chipscope cores utilize FPGA ResourcesBlock RAM: trigger and data storageSlice l