數(shù)字邏輯-第五章-常見(jiàn)數(shù)字模塊-更新-DDCA-Ch5-2課件

1、Digital Design and Computer Architecture, 2nd EditionChapter 5David Money Harris and Sarah L. Harris常見(jiàn)數(shù)字模塊Digital Design and Computer ArChapter 5 : TopicsIntroduction引言Arithmetic Circuits算術(shù)電路Number Systems數(shù)制系統(tǒng)Sequential Building Blocks 時(shí)序電路模塊Memory Arrays存儲(chǔ)器陣列Logic Arrays邏輯陣列Chapter 5 : TopicsIntrod

2、uctioDigital building blocks:數(shù)字模塊Gates, multiplexers, decoders, registers, arithmetic circuits, counters, memory arrays, logic arrays邏輯門電路、多路選擇器、譯碼器、寄存器、算術(shù)運(yùn)算電路、計(jì)算器、存儲(chǔ)器陣列、邏輯陣列Building blocks demonstrate hierarchy, modularity, and regularity:Hierarchy of simpler componentsWell-defined interfaces and f

3、unctionsRegular structure easily extends to different sizesIntroduction引言說(shuō)明了層次化、模塊化、規(guī)整化的原則復(fù)雜模塊可以用層次化的方法由更簡(jiǎn)單的模塊（如邏輯門電路、多路選擇器、譯碼器等）組成。每個(gè)模塊都有定義好的接口，當(dāng)?shù)讓訉?shí)現(xiàn)不重要時(shí)，可以被視為黑盒。每一個(gè)規(guī)整結(jié)構(gòu)的模塊都應(yīng)易于擴(kuò)展為不同規(guī)模。Digital building blocks:數(shù)字模塊In1-Bit Adders一位加法器圖5-1 1 位半加器圖5-3 1位全加器1-Bit Adders一位加法器圖5-1 1 位半加器圖1-Bit Adders一位加法器圖

4、5-1 1 位半加器圖5-3 1位全加器1-Bit Adders一位加法器圖5-1 1 位半加器圖1-Bit Adders一位加法器圖5-1 1 位半加器圖5-3 1位全加器1-Bit Adders一位加法器圖5-1 1 位半加器圖Types of carry propagate adders (CPAs):Ripple-carry (slow)Carry-lookahead (fast) 先行進(jìn)位加法器Prefix (faster) 前綴加法器Carry-lookahead and prefix adders faster for large adders but require more

5、hardware SymbolMultibit Adders (CPAs)多位加法器進(jìn)位傳播加法器的類型行波進(jìn)位加法器圖5-4 進(jìn)位傳播加法器對(duì)于大位數(shù)相加，先行進(jìn)位加法器和前綴加法器更快，但是需要更多的硬件Types of carry propagate adderChain 1-bit adders together連續(xù)串聯(lián)一位全加器Carry ripples through entire chain行波進(jìn)位通過(guò)整個(gè)鏈Disadvantage: slow缺點(diǎn)是速度慢Ripple-Carry Adder行波進(jìn)位加法器圖5-5 32位行波進(jìn)位加法器Chain 1-bit adders toge

6、ther連續(xù)串tripple = NtFA where tFA is the delay of a full adderRipple-Carry Adder Delay行波進(jìn)位加法器的延遲其中tFA是一個(gè)全加器的延遲Ripple-Carry Adder Delay行波進(jìn)位加法Compute carry out (Cout) for k-bit blocks using generate and propagate signals計(jì)算輸出進(jìn)位Cout 對(duì)k位塊用G和P兩個(gè)信號(hào)Some definitions:一些定義Column i produces a carry out by either

7、generating a carry out or propagating a carry in to the carry outGenerate (Gi) and propagate (Pi) signals for each column:Column i will generate a carry out if Ai AND Bi are both 1. Gi = Ai BiColumn i will propagate a carry in to the carry out if Ai OR Bi is 1.Pi = Ai + BiThe carry out of column i (

8、Ci) is: Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1Carry-Lookahead Adder先行進(jìn)位加法器如果Ai和Bi都是1，第i列產(chǎn)生一個(gè)輸出如果Ai或者Bi為1，第i列會(huì)產(chǎn)生一個(gè)進(jìn)位輸出如果加法器的第i列會(huì)產(chǎn)生一個(gè)進(jìn)位Gi，或者傳播進(jìn)位輸入Pi Ci-1 ，它就會(huì)產(chǎn)生進(jìn)位輸出Ci Compute carry out (Cout) for kStep 1: Compute Gi and Pi for all columns Step 2: Compute G and P for k-bit blocksStep 3: Cin propaga

9、tes through each k-bit propagate/generate blockCarry-Lookahead Addition先行進(jìn)位加法 由輸入的A，B算出每一位的G，P 計(jì)算k位塊的G和P (由各位的G，P算出每一位的GN:0，PN:0 ） 由每一位的GN：0，PN：0與Cin算出每一位的Cout，S。 其中第1，3步顯然是可以并行處理的，計(jì)算的主要復(fù)雜度集中在了第2步。Step 1: Compute Gi and Pi for Example: 4-bit blocks (G3:0 and P3:0) : G3:0 = G3 + P3 (G2 + P2 (G1 + P1G

10、0 ) P3:0 = P3P2 P1P0Generally, Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj ) Pi:j = PiPi-1 Pi-2PjCi = Gi:j + Pi:j Ci-1Carry-Lookahead Adder先行進(jìn)位加法器見(jiàn)中文書p173Example: 4-bit blocks (G3:0 an32-bit CLA with 4-bit Blocks由8個(gè)4位塊組成的32位先行進(jìn)位加法器圖5-6 32位先行進(jìn)位加法器（CLA）；4位CLA模塊32-bit CLA with 4-bit Blocks由8For N-bit CL

11、A with k-bit blocks:一個(gè)分解成k位塊的N位加法器延遲為 tCLA = tpg + tpg_block + (N/k 1)tAND_OR + ktFAtpg : delay to generate all Pi, Gi 為單獨(dú)一個(gè)生成產(chǎn)生信號(hào)P和傳播G的門電路（一個(gè)單獨(dú)的AND或者OR門電路）tpg_block :delay to generate all Pi:j, Gi:j 為在k位塊中生成產(chǎn)生信號(hào)Pi:j和輸出信號(hào)Gi:j的延遲tAND_OR :delay from Cin to Cout of final AND/OR gate in k-bit CLA block

12、為在k位CLA塊中Cin從AND/OR邏輯到Cout的延遲An N-bit carry-lookahead adder is generally much faster than a ripple-carry adder for N 16Carry-Lookahead Adder Delay先行進(jìn)位加法器的延遲當(dāng)N 16時(shí)，先行進(jìn)位加法器一般總會(huì)比行波進(jìn)位加法器塊很多For N-bit CLA with k-bit blockSubtracter減法器圖5-9 減法器；電路符號(hào)、實(shí)現(xiàn)減法非常簡(jiǎn)單：改變減數(shù)的符號(hào)，然后做加法。改變二進(jìn)制補(bǔ)碼的符號(hào)就是翻轉(zhuǎn)所有的位，然后加一Subtracter減法

13、器圖5-9 減法器；電路符號(hào)、實(shí)現(xiàn)Comparator: Equality相等比較器圖5-11 4位相等比較器；電路符號(hào)，實(shí)現(xiàn)電路符號(hào)實(shí)現(xiàn)相等相等Comparator: Equality相等比較器圖5-11Copyright 2007 Elsevier5-Comparator: Less Than小于比較器圖5-12 N位數(shù)量比較器Copyright 2007 Elsevier5-17Copyright 2007 Elsevier5-F2:0Function000A & B001A | B010A + B011not used100A & B101A | B110A - B111SLTArit

14、hmetic Logic Unit (ALU)算術(shù)邏輯單元圖5-14 算術(shù)邏輯單元電路符號(hào)表5-1 ALU操作SLT：小于置位操作，set if less thanCopyright 2007 Elsevier5-18Copyright 2007 Elsevier5-F2:0Function000A & B001A | B010A + B011not used100A & B101A | B110A - B111SLTALU Design算術(shù)邏輯單元設(shè)計(jì)圖5-15 N位算術(shù)邏輯單元表5-1 ALU操作SLT：小于置位操作，set if less thanCopyright 2007 Elsev

15、ier5-19Copyright 2007 Elsevier5-Configure 32-bit ALU for SLT operation: A = 25 and B = 32Set Less Than (SLT) Example圖5-15 N位算術(shù)邏輯單元小于置位操作SLT例子 見(jiàn)p179，例5.3配置一個(gè)32位算術(shù)邏輯單元用于SLT操作，假設(shè)A=25，B=32，寫出控制信號(hào)和輸出Y。Copyright 2007 Elsevier5-20Copyright 2007 Elsevier5-Configure 32-bit ALU for SLT operation: A = 25 and B

16、 = 32A B, so Y should be 32-bit representation of 1 (0 x00000001)F2:0 = 111F2 = 1 (adder acts as subtracter), so 25 - 32 = -7-7 has 1 in the most significant bit (S31 = 1)F1:0 = 11 multiplexer selects Y = S31 (zero extended) = 0 x00000001.Set Less Than (SLT) Example小于置位操作SLT例子圖5-15 N位算術(shù)邏輯單元Copyright

17、 2007 Elsevier5-21Copyright 2007 Elsevier5-Logical shifter: shifts value to left or right and fills empty spaces with 0sEx: 11001 2 =Ex: 11001 2 =Ex: 11001 2 =Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other endEx: 11001 ROR 2 =Ex: 11001 ROL 2 =Shifter

18、s移位器 見(jiàn)中文書p179邏輯移位器：左移或者右移數(shù)，以0填充空位算術(shù)移位器：和邏輯移位器一樣，不過(guò)在算術(shù)右移時(shí)會(huì)把原先數(shù)據(jù)的最高標(biāo)志位填充在新數(shù)據(jù)的最高標(biāo)志位上。循環(huán)移位器：循環(huán)轉(zhuǎn)換數(shù)字，從一端移走的位重新填充到另一端的空位上。Copyright 2007 Elsevier5- 2 = 00110Ex: 11001 2 = 11110Ex: 11001 2 = 00100Rotator: 循環(huán)移位器Ex: 11001 ROR 2 = 01110Ex: 11001 ROL 2 = 00111Shifters移位器Logical shifter: 邏輯移位器ShiftersShifter Des

19、ign移位器設(shè)計(jì)圖5-16 4位移位器，左移Shifter Design移位器設(shè)計(jì)圖5-16 4位移位A N = A 2N Example: 00001 2 = 00100 (1 22 = 4)Example: 11101 N = A 2N Example: 01000 2 = 00010 (8 22 = 2)Example: 10000 2 = 11100 (-16 22 = -4)Shifters as Multipliers, Dividers移位器相當(dāng)于乘法、除法N位左移相當(dāng)于對(duì)一個(gè)數(shù)乘以2N倍N位的算術(shù)右移相當(dāng)于對(duì)一個(gè)數(shù)除以2N 。A N = A 2N Shifters asPart

20、ial products formed by multiplying a single digit of the multiplier with multiplicandShifted partial products summed to form resultMultipliers乘法圖5-17 乘法；十進(jìn)制，二進(jìn)制部分積為乘數(shù)的一位乘以被乘數(shù)的所有位。移位這些部分積，并將它們相加就可以得到最后結(jié)果。見(jiàn)中文書p180Partial products formed by mul4 x 4 Multiplier 4*4乘法器圖5-18 4*4乘法器；符號(hào)，原理，實(shí)現(xiàn)4 x 4 Multiplie

21、r 4*4乘法器圖5-18 Numbers we can represent using binary representations我們可以用二進(jìn)制表示數(shù)字Positive numbers正數(shù)Unsigned binary無(wú)符號(hào)二進(jìn)制數(shù)Negative numbers負(fù)數(shù)Twos complement二進(jìn)制補(bǔ)碼Sign/magnitude numbers帶符號(hào)的原碼What about fractions?Number Systems數(shù)制系統(tǒng)小數(shù)部分有符號(hào)定點(diǎn)數(shù)可以用二進(jìn)制補(bǔ)碼或者帶符號(hào)的原碼表示Numbers we can represent usingTwo common notatio

22、ns:兩種常用表示法Fixed-point: binary point fixedFloating-point: binary point floats to the right of the most significant 1Numbers with Fractions帶小數(shù)的數(shù)- 定點(diǎn)數(shù)表示法有一個(gè)位于整數(shù)和小數(shù)位之間的隱含二進(jìn)制小數(shù)點(diǎn)，類似于通常十進(jìn)制數(shù)中位于整數(shù)和小數(shù)位之間的十進(jìn)制小數(shù)點(diǎn)。- 浮點(diǎn)數(shù)：二進(jìn)制浮點(diǎn)的最右邊用1位表示符號(hào)。浮點(diǎn)數(shù)與科學(xué)計(jì)數(shù)法相似，它解決了整數(shù)和小數(shù)位長(zhǎng)度固定的限制，允許表示一個(gè)非常大或者非常小的數(shù)。如科學(xué)計(jì)數(shù)法一樣，浮點(diǎn)數(shù)包含了符號(hào)、尾數(shù)、基數(shù)和階碼。Tw

23、o common notations:兩種常用表示法Nu6.75 using 4 integer bits and 4 fraction bits:Binary point is implied二進(jìn)制小數(shù)點(diǎn)隱含了Fixed-Point Numbers定點(diǎn)數(shù)系統(tǒng)6.75用4位整數(shù)和4位小數(shù)位表示圖5-21 6.75用4個(gè)整數(shù)位和4個(gè)小數(shù)點(diǎn)位表示的定點(diǎn)表示6.75 using 4 integer bits and Represent 7.510 using 4 integer bits and 4 fraction bits.Fixed-Point Number Example定點(diǎn)數(shù)系統(tǒng)例子Rep

24、resent 7.510 using 4 integeRepresent 7.510 using 4 integer bits and 4 fraction bits.01111000Fixed-Point Number Example定點(diǎn)數(shù)系統(tǒng)例子Represent 7.510 using 4 integeRepresentations:表示Sign/magnitude符號(hào)數(shù)值Twos complement二進(jìn)制補(bǔ)碼Example: Represent -7.510 using 4 integer and 4 fraction bitsSign/magnitude:Twos compleme

25、nt:Signed Fixed-Point Numbers帶符號(hào)的定點(diǎn)數(shù)Representations:表示Signed FixedRepresentations:表示Sign/magnitude符號(hào)數(shù)值Twos complement二進(jìn)制補(bǔ)碼Example: Represent -7.510 using 4 integer and 4 fraction bitsSign/magnitude:符號(hào)數(shù)值11111000Twos complement:補(bǔ)碼1. +7.5:011110002. Invert bits: 10000111 3. Add 1 to lsb:+ 1 10001000Sig

26、ned Fixed-Point Numbers帶符號(hào)的定點(diǎn)數(shù)Representations:表示Signed FixedSimilar to decimal scientific notationFor example, write 27310 in scientific notation:273 = 2.73 102In general, a number is written in scientific notation as: M BEM = mantissa尾數(shù)B = base基數(shù)E = exponent階碼In the example, M = 2.73, B = 10, and E

27、 = 2Floating-Point Numbers浮點(diǎn)數(shù)系統(tǒng)浮點(diǎn)數(shù)與科學(xué)計(jì)數(shù)法相似。它解決了整數(shù)和小數(shù)位長(zhǎng)度固定的限制，允許表示非常大或者非常小的數(shù)。浮點(diǎn)數(shù)包含了符號(hào)，尾數(shù)，基數(shù)和階碼Similar to decimal scientific Example: represent the value 22810 using a 32-bit floating point representationWe show three versions final version is called the IEEE 754 floating-point standardFloating-Point

28、Numbers浮點(diǎn)數(shù)系統(tǒng) 見(jiàn)中文書p184，例184符號(hào)階碼尾數(shù)Floating-Point Numbers浮點(diǎn)數(shù)系統(tǒng) Convert decimal to binary (dont reverse steps 1 & 2!):22810 = 111001002 Write the number in “binary scientific notation”:111001002 = 1.110012 27 Fill in each field of the 32-bit floating point number:The sign bit is positive (0)The 8 expone

29、nt bits represent the value 7The remaining 23 bits are the mantissaFloating-Point Representation 1符號(hào)階碼尾數(shù)浮點(diǎn)數(shù)表示Convert decimal to binary (donFirst bit of the mantissa is always 1:22810 = 111001002 = 1.11001 27 So, no need to store it: implicit leading 1Store just fraction bits in 23-bit fieldFloating-

30、Point Representation 2浮點(diǎn)數(shù)表示符號(hào)階碼小數(shù)First bit of the mantissa is aBiased exponent: bias = 127 (011111112) Biased exponent = bias + exponentExponent of 7 is stored as:127 + 7 = 134 = 0 x100001102The IEEE 754 32-bit floating-point representation of 22810 in hexadecimal: 0 x43640000Floating-Point Represen

31、tation 3浮點(diǎn)數(shù)表示符號(hào)偏置階碼小數(shù)Biased exponent: bias = 127 (0Write -58.2510 in floating point (IEEE 754)Floating-Point Example浮點(diǎn)數(shù)例子Write -58.2510 in floating poiWrite -58.2510 in floating point (IEEE 754)Convert decimal to binary: 58.2510 = 111010.012Write in binary scientific notation:1.1101001 25Fill in fie

32、lds:Sign bit: 1 (negative)8 exponent bits: (127 + 5) = 132 = 10000100223 fraction bits: 110 1001 0000 0000 0000 0000in hexadecimal: 0 xC2690000Floating-Point Example浮點(diǎn)數(shù)例子符號(hào)偏置階碼小數(shù)Write -58.2510 in floating poiNumberSignExponentFraction0X000000000000000000000000000000001111111100000000000000000000000-

33、 11111111100000000000000000000000NaNX11111111non-zeroFloating-Point: Special Cases浮點(diǎn)數(shù)：特殊情況數(shù)符號(hào)階碼小數(shù)NumberSignExponentFraction0X00Single-Precision:單精度32-bit1 sign bit, 8 exponent bits, 23 fraction bitsbias = 127Double-Precision:雙精度64-bit1 sign bit, 11 exponent bits, 52 fraction bitsbias = 1023Floating-

34、Point Precision浮點(diǎn)數(shù)精度見(jiàn)中文書p185Single-Precision:單精度Floating-POverflow: number too large to be represented上溢Underflow: number too small to be represented下溢Rounding modes: 舍入的模式有DownUpToward zeroTo nearestExample: round 1.100101 (1.578125) to only 3 fraction bitsDown: 1.100Up: 1.101Toward zero:1.100To ne

35、arest:1.101 (1.625 is closer to 1.578125 than 1.5 is)Floating-Point: Rounding浮點(diǎn)數(shù)：舍入Overflow: number too large tExtract exponent and fraction bits分開階碼和小數(shù)位Prepend leading 1 to form mantissa加上前導(dǎo)1，形成尾數(shù)Compare exponents比較階碼Shift smaller mantissa if necessary如果需要，對(duì)較小的尾數(shù)移位Add mantissas位數(shù)相加Normalize mantiss

36、a and adjust exponent if necessary 規(guī)整化尾數(shù)，并在需要時(shí)調(diào)整階碼8. Round result結(jié)果舍入9. Assemble exponent and fraction back into floating-point format把階碼和小數(shù)組合成浮點(diǎn)數(shù)Floating-Point Addition浮點(diǎn)數(shù)加法Extract exponent and fraction Increments on each clock edgeUsed to cycle through numbers. For example, 000, 001, 010, 011, 100

37、, 101, 110, 111, 000, 001Example uses:Digital clock displaysProgram counter: keeps track of current instruction executingCounters計(jì)數(shù)器圖5-30 計(jì)數(shù)器電路符號(hào)圖5-31 N位計(jì)數(shù)器N位二進(jìn)制計(jì)數(shù)器是包含了時(shí)鐘和復(fù)位輸入，N位輸出Q的時(shí)序算術(shù)電路。計(jì)數(shù)器是產(chǎn)生特定的二進(jìn)制計(jì)數(shù)序列的電路Increments on each clock edgeCImplementation:Shift a new bit in on each clock edgeShift a bi

38、t out on each clock edge同時(shí)，移出一位Serial-to-parallel converter: converts serial input (Sin) to parallel output (Q0:N-1)Shift Registers移位寄存器Symbol:圖5-33 移位寄存器電路符號(hào)圖5-34 移位寄存器電路原理圖在每一個(gè)時(shí)鐘上升沿，會(huì)從Sin移入一個(gè)新的位移位寄存器可以看作串行到并行的轉(zhuǎn)換器Implementation:Shift a new bitEfficiently store large amounts of data3 common types:Dy

39、namic random access memory (DRAM)動(dòng)態(tài)隨機(jī)存儲(chǔ)器Static random access memory (SRAM)靜態(tài)隨機(jī)存儲(chǔ)器Read only memory (ROM)只讀存儲(chǔ)器M-bit data value read/ written at each unique N-bit addressMemory Arrays存儲(chǔ)器陣列圖5-38 一般存儲(chǔ)器陣列電路符號(hào)存儲(chǔ)器陣列：有效存儲(chǔ)大量數(shù)據(jù)地址陣列存儲(chǔ)器由一個(gè)二維存儲(chǔ)器單元陣列構(gòu)成。存儲(chǔ)器可以讀取或者寫入內(nèi)容到陣列中的一行。這一行由地址指定。讀出或者寫入的值稱為數(shù)據(jù)。Efficiently store l

40、arge amount2-dimensional array of bit cells Each bit cell stores one bitN address bits and M data bits:2N rows and M columnsDepth: number of rows (number of words)Width: number of columns (size of word)Array size: depth width = 2N M Memory Arrays存儲(chǔ)器陣列圖5-38 一般存儲(chǔ)器陣列電路符號(hào)圖5-39 4*3存儲(chǔ)器陣列；電路符號(hào)，功能存儲(chǔ)器由一個(gè)二維存儲(chǔ)

41、器單元陣列構(gòu)成。一個(gè)有N位地址和M位數(shù)據(jù)的陣列就有2N行和M列。陣列的深度是行數(shù)，寬度是列數(shù)，也稱為字大小。陣列的大小就是深度*寬度2-dimensional array of bit cel22 3-bit arrayNumber of words: 4Word size: 3-bitsFor example, the 3-bit word stored at address 10 is 100Memory Array Example存儲(chǔ)器陣列例子圖5-39 4*3存儲(chǔ)器陣列；電路符號(hào)，功能22 3-bit arrayMemory Array EMemory Arrays存儲(chǔ)器陣列圖5-40

42、 32Kb陣列：深度=210=1024字，寬度=32位Memory Arrays存儲(chǔ)器陣列圖5-40 32Kb陣ZMemory Array Bit Cells存儲(chǔ)器陣列位單元圖5-41 位單元字線存儲(chǔ)位位線ZMemory Array Bit Cells存儲(chǔ)器陣列位單01ZZMemory Array Bit Cells存儲(chǔ)器陣列位單元圖5-41 位單元字線存儲(chǔ)位位線01ZZMemory Array Bit Cells存儲(chǔ)器陣Wordline: 字線like an enablesingle row in memory array read/writtencorresponds to unique

43、addressonly one wordline HIGH at onceMemory Array存儲(chǔ)器陣列圖5-42 4*3存儲(chǔ)器陣列存儲(chǔ)器陣列以位單元構(gòu)成的陣列組成，其中每個(gè)位單元存儲(chǔ)1位數(shù)據(jù)。每一個(gè)位單元與特定字線和特定位線相連。對(duì)于每一個(gè)地址位的組合，存儲(chǔ)器將字線設(shè)置為高電平，并激活此行中的位單元Wordline: 字線Memory Array存儲(chǔ)器陣列圖Random access memory (RAM): volatileRead only memory (ROM): nonvolatileTypes of Memory存儲(chǔ)器類型隨機(jī)訪問(wèn)存儲(chǔ)器：是易失的，即關(guān)掉電源時(shí)就會(huì)丟失數(shù)據(jù)只

44、讀存儲(chǔ)器：是非易失的，即沒(méi)有電源時(shí)也可以保存數(shù)據(jù)Random access memory (RAM): voVolatile: loses its data when power offRead and written quickly快速地讀寫Main memory in your computer is RAM (DRAM)Historically called random access memory because any data word accessed as easily as any other (in contrast to sequential access memorie

45、s such as a tape recorder)RAM: Random Access Memory隨機(jī)訪問(wèn)存儲(chǔ)器易失的RAM和ROM因?yàn)橐恍v史的原因獲得現(xiàn)在的名字，但是現(xiàn)在也不再有意義了。RAM之所以稱為隨機(jī)訪問(wèn)存儲(chǔ)器，是因?yàn)樵L問(wèn)任何數(shù)據(jù)字的延遲都是相同。ROM之所以稱為只讀存儲(chǔ)器，因?yàn)樵跉v史上它只能讀，而不能被寫入?，F(xiàn)在大部分ROM可以讀也可以寫。Volatile: loses its data when Nonvolatile: retains data when power offRead quickly, but writing is impossible or slow讀快，但

46、是不能寫或?qū)懙穆鼺lash memory in cameras, thumb drives, and digital cameras are all ROMsHistorically called read only memory because ROMs were written at manufacturing time or by burning fuses. Once ROM was configured, it could not be written again. This is no longer the case for Flash memory and other types

47、 of ROMs.ROM: Read Only Memory只讀存儲(chǔ)器非易失的Nonvolatile: retains data whenDRAM (Dynamic random access memory)SRAM (Static random access memory)Differ in how they store data:DRAM uses a capacitorSRAM uses cross-coupled invertersTypes of RAM RAM的類型- 動(dòng)態(tài)隨機(jī)訪問(wèn)存儲(chǔ)器DRAM- 靜態(tài)隨機(jī)訪問(wèn)存儲(chǔ)器SRAM- 動(dòng)態(tài)RAM以電容充放電存儲(chǔ)數(shù)據(jù)，靜態(tài)RAM使用交叉耦合

48、的反向器對(duì)存儲(chǔ)DRAM (Dynamic random access meData bits stored on capacitor數(shù)據(jù)位存儲(chǔ)在電容上Dynamic because the value needs to be refreshed (rewritten) periodically and after read:Charge leakage from the capacitor degrades the valueReading destroys the stored valueDRAM動(dòng)態(tài)隨機(jī)訪問(wèn)存儲(chǔ)器圖5-45 DRAM存儲(chǔ)值充電泄漏讀會(huì)破壞存儲(chǔ)在電容中的位值Data bits

49、 stored on capacitor數(shù)DRAM動(dòng)態(tài)隨機(jī)訪問(wèn)存儲(chǔ)器圖5-45 DRAM存儲(chǔ)值當(dāng)電容充電到Vdd時(shí)，存儲(chǔ)位為1當(dāng)放電到GND時(shí)，存儲(chǔ)位為0DRAM動(dòng)態(tài)隨機(jī)訪問(wèn)存儲(chǔ)器圖5-45 DRAM存儲(chǔ)值當(dāng)電容SRAM靜態(tài)隨機(jī)訪問(wèn)存儲(chǔ)器圖5-46 SRAM位單元SRAM靜態(tài)隨機(jī)訪問(wèn)存儲(chǔ)器圖5-46 SRAM位單元DRAM bit cell:SRAM bit cell:Memory Arrays Review存儲(chǔ)器陣列回顧圖5-42 4*3存儲(chǔ)器陣列DRAM bit cell:SRAM bit cell:MeROM: Dot Notation圖5-49 4*3的ROM：點(diǎn)表示法圖5-48 包含

50、0和1的ROM位單元隨機(jī)訪問(wèn)存儲(chǔ)器：點(diǎn)表示法ROM: Dot Notation圖5-49 4*3的ROROM Storage只讀存儲(chǔ)器的存儲(chǔ)圖5-49 4*3的ROM：點(diǎn)表示法ROM Storage只讀存儲(chǔ)器的存儲(chǔ)圖5-49 4*3的Data2 = A1 A0Data1 = A1 + A0Data0 = A1A0ROM Logic只讀存儲(chǔ)器的邏輯圖5-49 4*3的ROM：點(diǎn)表示法Data2 = A1 A0ROM Logic只讀存儲(chǔ)器的Implement the following logic functions using a 22 3-bit ROM:X = ABY = A + BZ =

51、A BExample: Logic with ROMs例子：帶只讀存儲(chǔ)器的邏輯Implement the following logic Implement the following logic functions using a 22 3-bit ROM:X = ABY = A + BZ = A BExample: Logic with ROMs例子：帶只讀存儲(chǔ)器的邏輯Implement the following logic Data2 = A1 A0Data1 = A1 + A0Data0 = A1A0Logic with Any Memory Array帶任意存儲(chǔ)器陣列的邏輯Data2 = A1 A0Logic with Any Implement the following logic functions using a 22 3-bit memory array:X = ABY = A + BZ = A BLogic with Memory Arrays帶存儲(chǔ)器陣列的邏輯Implement the following logic Impl