大規(guī)模數(shù)字集成電路設計第二章VHDL語言程序的基本結(jié)構(gòu)課件

1、大規(guī)模數(shù)字集成電路設計第二章VHDL語言程序的基本結(jié)構(gòu)本章要點VHDL程序的宏觀結(jié)構(gòu)；實體的基本格式及其在VHDL硬件設計中的應用構(gòu)造體的基本格式及其在VHDL硬件設計中的基本功能庫的實用意義及使用方法。 2.1 VHDL程序組成部分及其功能VHDL程序?qū)嶓w（Entity）構(gòu)造體（Architecture）配置（Configuration）包集合（Package）庫（Library）設計共享部分需編寫的部分VHDL描述的總體結(jié)構(gòu)2.2 實體實體說明的結(jié)構(gòu)ENTITY 實體名 IS【類屬參數(shù)說明】；【端口說明】；END 實體名；2.2 實體說明 端口說明1）端口名2）端口方向3）數(shù)據(jù)類型2.3

2、構(gòu)造體 構(gòu)造體的結(jié)構(gòu)ARCHITECTURE 構(gòu)造體名 OF 實體名 IS【定義語句】內(nèi)部信號、常數(shù)、數(shù)據(jù)類型等的定義；BEGIN【并行處理語句】；END 構(gòu)造體名；2.3 構(gòu)造體 1）構(gòu)造體的命名 2）定義語句 3）并行處理語句2.3 構(gòu)造體 一個完整的構(gòu)造體由兩個基本層次組成：2) 描述實體邏輯行為的，以各種不同的描述風格表示的功能描述語句。1）對數(shù)據(jù)類型，常數(shù)，信號，子程序和元件等元素的說明部分。【例1】 二選一選擇器ANDNOTANDORD1SELD0Qtmp1tmp2MUX2ID0Entity mux2id0 isPort(d0,d1,sel : in bit;q : out bit

3、);End mux2id0;Architecture struc of mux isBeginprocess(d0,d1,sel)variable tmp1,tmp2,tmp3 : bit;begintmp1:=d0 AND sel;tmp2:=d1 AND(NOT sel);q=tmp1 OR tmp2;end process;End struc;【例1】 二選一選擇器【例 1-2】 二選一選擇器的構(gòu)造體說明(續(xù)) ARCHITECTURE connect OF mux IS- 構(gòu)造體定義BEGIN - 構(gòu)造體開始標記 PROCESS (d0, d1, sel) - 進程 VARIABLE

4、tmp1, tmp2, tmp3: BIT; - 變量的聲明 BEGIN- 進程開始標記 tmp1 := d0 AND sel;- 變量賦值語句 tmp2 := d1 AND (NOT sel);- 變量賦值語句 q = tmp1 OR tmp2; - 信號賦值語句 END PROCESS;- 進程結(jié)束END connect;- 構(gòu)造體結(jié)束Putting it all together Packages are a convenient way of storing and using information throughout an entire model. Packages consi

5、st of: Package Declaration (Required)Type declarationsSubprograms declarations Package Body (Optional)Subprogram definitions VHDL has two built-in Packages Standard TEXTIO2.4 包集合（Package）2.5 庫Contains a package or a collection of packages.Resource Libraries Standard Package IEEE developed packages A

6、ltera Component packages Any library of design units that are referenced in a design.Working Library Library into which the unit is being compiled.必須放在VHDL程序最前面;在VHDL程序中，可以有多個庫，庫和庫之間相互獨立; All packages must be compiled Implicit Libraries Work STD Note: Items in these packages do not need to be refere

7、nced,they are implied. LIBRARY Clause Defines the library name that can be referenced. Is a symbolic name to path/directory. Defined by the Compiler Tool. USE Clause Specifies the package and object in the library that you have specified in the Library clause.2.5 庫LIBRARY STD Contains the following

8、packages:standard ( Types: Bit, Boolean, Integer, Real, and Time. All operator functions to support types)textio (File operations) An implicit library (built-in)Does not need to be referenced in VHDL designTypes defined in Standard Package Type BIT 2 logic value system (0, 1)signal a_temp : bit; BIT

9、_VECTOR array of bitssignal temp : bit_vector(3 downto 0);signal temp : bit_vector(0 to 3) ; Type BOOLEAN (false, true) Integer Positive and negative values in decimalsignal int_tmp : integer; - 32 bit numbersignal int_tmp1 : integer range 0 to 255; -8 bit numberNote: Standard package has other type

10、sLIBRARY IEEEContains the following packages: std_logic_1164 (std_logic types & related functions) std_logic_arith (arithmetic functions) std_logic_signed (signed arithmetic functions) std_logic_unsigned (unsigned arithmetic functions)Types defined in std_logic_1164 Package Type STD_LOGIC 9 logic va

11、lue system (U, X, 0, 1, Z, W, L, H, -) W, L, H” weak values (Not supported by Synthesis) X - used for unknown Z - (not z) used for tri-state - Dont Care Resolved type: supports, signals with multiple drives. Type STD_ULOGIC Same 9 value system as STD_LOGIC Unresolved type: Does not support multiple signal drives.Error will occur.【例2】二選一選擇器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux ISGENERIC (m: TIME :=1ns);PORT (d0,d1: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;sel: IN STD_LOGIC ;