測控大二-數(shù)電實驗3.5testbench簡介

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C實例：一位二進制全加器VHDL描述(--端口說明A

:

INSTD_LOGIC;B

:

IN

STD_LOGIC;Ci_1

:

IN

STD_LOGIC;Ci

:

OUT

STD_LOGIC;Si:

OUT

STD_LOGIC--庫調(diào)用說明--結(jié)構(gòu)體開始LIBRARY

ieee;USE

ieee.std_logic_1164.all;

--程序包調(diào)用說明ENTITY

adder

IS

--實體開始PORT);END

adder;

--實體結(jié)束ARCHITECTURE

adder_architecture

OF

adder

ISBEGINSi<=(not

A

and

not

B

and

Ci_1)

or

(not

A

and

B

and

not

Ci_1)

or

(Aand

not

B

and

not

Ci_1)or

(A

and

B

and

Ci_1);--功能描述Ci<=(A

and

B)

or

(B

and

Ci_1)

or

(Ci_1

and

A);END

adder_architecture;

--結(jié)構(gòu)體結(jié)束i1i1i1i1i1

ABC

ABC

ABCii

i1C

AB

AC

BCS

ABCFX

C實例：一位二進制全加器VHDL

TestbenchLIBRARY

ieee;

--庫調(diào)用說明USE

ieee.std_logic_1164.all;

--程序包調(diào)用說明ENTITY

add1bit_bt

ISEND

add1bit_bt;ARCHITECTURE

behavior

OF

add1bit_bt

ISCOMPONENT

add1bitPORT(A

:IN

std_logic;B

:

IN

std_logic;Ci_1

:

IN

std_logic;S

:

OUT

std_logic;Ci

:

OUT

std_logic);END

COMPONENT;signal

A

:

std_logic

:=

'0';signal

B

:

std_logic

:=

'0';signal

Ci_1

:

std_logic

:=

'0';signal

S

:

std_logic;signal

Ci

:

std_logic;FX

C實例：一位二進制全加器VHDL

TestbenchBEGINuut:

add1bit

PORT

MAP( A

=>A,B

=>

B,Ci_1

=>

Ci_1,S

=>

S,Ci

=>

Ci

);tb:

processbeginA<='0';B<='0';Ci_1<='0';Wait

for

100ns;A<='1';B<='0';Ci_1<='0';Wait

for

100ns;A<='0';B<='1';Ci_1<='0';Wait

for

100ns;FX

C實例：一位二進制全加器VHDL

TestbenchA<='1';B<='1';Ci_1<='0';Wait

for

100ns;A<='0';B<='0';Ci_1<='1';Wait

for

100ns;A<='1';B<='0';Ci_1<='1';Wait

for

100ns;A<='0';B<='1';Ci_1<='1';Wait

for

100ns;A<='1';B<='1';Ci_1<='1';Wait

for

100ns;endprocess;END;FCX實例：激勵的另法tb

:PROCESSvariable

tmp

:

STD_LOGIC_VECTOR

(2

downto

0);BEGINLP1:for

i

in

0

to

7

looptmp:=conv_std_logic_vector(i,3);a<=