數(shù)字邏輯雙語-courseware6analysis and synthesis of synchronous sequential logic circuits

Analysis&DesignofSynchronousSequentialLogicCircuitsDigitalLogic2ConceptsofSequentialCircuitsClassificationofSequentialCircuitsSynchronousSequentialCircuits(同步時序電路):Allflip-flopsinsystemarecontrolledbyoneglobalclock

signal.

Thatiswhatwewilldiscussinthischapter.AsynchronousSequentialCircuits(異步時序電路):Allflip-flopsarenotdrivenbyoneclocksignal.Thatis,thetransitionfromonestatetoanotherisinitiatedbythechangeintheprimaryinputs;thereisnoexternalsynchronisation(無外部同步機(jī)制).DigitalLogic3ConceptsofSequentialCircuitsTwoBasicModelsMealy(米里型):TheoutputisafunctionofPresentStates&PresentInputs;Moore(摩爾型):Theoutputcanchangeonlywhenthestatechangesandhavenothingtodowiththeinputs.OutputonlydependsonPresentStates.Mealy&MoorearebothScientists’name.DigitalLogic4ConceptsofSequentialCircuitsTwoTypicalApplicationsAnalysis(分析):Withgivencircuit,tellwhatdoesitdo?Design/Synthesis(設(shè)計/綜合):Givenspecificationofcircuit,developdesigns.DigitalLogic5SomeImportantConceptsDrivingEquation(ControlEquation,ExcitingEquation)(驅(qū)動方程)TheinputofFlip-Flops,suchas:J=….;K=….;CharacteristicEquation(特征方程)BelongstooneparticularFlip-Flop,suchasQn+1=D;Qn+1=JQ(n)’+K’Q(n);StateEquation(狀態(tài)方程)Equationdescribingtherelationshipofpresentstate(現(xiàn)態(tài))&nextstate(次態(tài))DigitalLogic6SomeImportantConceptsStatetransitiontable(狀態(tài)轉(zhuǎn)移表)Statetransitiondiagram(狀態(tài)轉(zhuǎn)移圖)XPresentStateNextStateYQ1(n)Q0(n)Q1(n+1)Q0(n+1)0000110110110111110011001100100010011111010/1000110110/10/10/11/01/11/11/0Input/outputInputsOutputsDigitalLogic7StepsofAnalysisofSynchronousSequentialCircuitsGivenCircuitsDerivetheOutputEquation&DrivingEquationsGivetheState

Transition

Table/

diagramFigureouttheStateTransitionEquationTiming

diagramExplainTheLogicFunctionThat’swhatwehaveThis’sourtargetWecaneasilygetweneedittoanalyzeDigitalLogic8Example1(Analysis)(Indetail)1,Derivethedrivingequation/excitingequation(驅(qū)動方程/激勵方程)accordingtocircuitdiagramDrivingequationisjusttheexpressionofinputterminalofFlip-Flops.DigitalLogic9Example1(Indetail)1,Derivetheoutputequations(輸出方程)Thesocalledoutputequationisjusttheexpressionofoutputterminalofcircuit.DigitalLogic10Example1(Indetail)2,Derivethestateequation(狀態(tài)方程)(ornext-stateequation)byconvertingtheseexcitingequationsintoflip-flops’characteristicequations(特征方程)Thesearestateequations,accordingtothese,wecanderivetheSTT(statetransitiontable).DigitalLogic11Example1(Indetail)3,Convertthesenext-stateequationsintostatetransitiontable(狀態(tài)轉(zhuǎn)移表)PresentState(現(xiàn)態(tài))NextState(次態(tài))YQ2nQ1nQ0nQ2n+1Q1n+1Q0n+100000100010110010101001111101000001101010111010001111100Whichisthebettersequenceofcalc…DigitalLogic12Example1(Indetail)3,Drawthestatetransitiondiagram(狀態(tài)轉(zhuǎn)移圖)PresentState(現(xiàn)態(tài))NextState(次態(tài))YQ2nQ1nQ0nQ2n+1Q1n+1Q0n+100000100010110010101001111101000001101010111010001111100001/0/0011/0111/0110/0100000/1notinnotin/1010101/0DrawSTDItisaninvalidloop(無效循環(huán))DigitalLogic13Example1(Indetail)/1010101/0Question:Canthissystemself-startup?Answer:No,ifsystemgetintoinvalidloop,itcannotcomebacktotherightstateautomatically.3,Drawthestatetransitiondiagram(狀態(tài)轉(zhuǎn)移圖)DigitalLogic14Example1(Indetail)4,Drawtheconclusionaboutthecircuits001/0/0011/0111/0110/0100/1000GrayCodeof0-5:000→001→011→111→110→100→000→…SoitisaModulo-6counterwithGraycode(格雷碼表示的模6計數(shù)器).DigitalLogic15Example1(Indetail)5,Furthermore,wecandrawthetimingdiagram(時序圖).Inthisexample,weassumetheoriginalstateofQ2,Q1,Q0

are000.Q2Q1Q0:000→001→011→111→110→100→000→…negativeedge/fallingedgetriggered(下降沿觸發(fā)).DigitalLogic16Example1(Indetail)5,ResultDiagram1(效果圖)CPQ0Q1Q2YDigitalLogic17Example2(Analysis)(Insteps)1,Derivethedrivingequationsandoutputequations,asfollowingDigitalLogic18Example2(Insteps)2,Derivethestateequations1,DerivethedrivingequationsandoutputequationsasfollowingDigitalLogic19Example2(Insteps)3,Statetransitiontable/diagramXPresentStateNextStateYQ1(n)Q0(n)Q1(n+1)Q0(n+1)000011011011011111001100110010001001111101Whiledoingthis,becareful.DigitalLogic20Example2(Insteps)XPresentStateNextStateYQ1(n)Q0(n)Q1(n+1)Q0(n+1)0000110110110111110011001100100010011111010/1000110110/10/10/11/01/11/11/00/1:‘/’前表示輸入X,后表示輸出Y3,Statetransitiontable/diagramDigitalLogic21Example2(Insteps)4,Drawtheconclusion/DetailthelogicfunctionWhenX＝0,StatechangesasfollowingatCPedge: 00→01→10→11→00→…WhenX＝1,StatechangesasfollowingatCPedge: 00→11→10→01→00→…Itisa2-bitup/downsynchronouscounter(2位同步可逆計數(shù)器).DigitalLogic22Example2(Insteps)5,Drawthetimingdiagram0/1000110110/10/10/11/01/11/11/0DigitalLogic23Example3(Analysis)(Insteps)1,DrivingequationsandoutputequationsareasfollowingDigitalLogic24Example3(Insteps)2,DerivethestateequationsDigitalLogic25Example3(Insteps)3,Statetransitiontable/diagramPresentState(現(xiàn)態(tài))NextState(次態(tài))YQ3(n)Q2(n)Q1(n)Q3(n+1)Q2(n+1)Q1(n+1)00000100010100010011001110001001010101110011000011110001EAC:ExcelaidedCalculatingDigitalLogic26Example3(Insteps)3,Statetransitiontable/diagram000001010011100101110111Here,outputYisomitted;State“111”isnotinvalidloop,but

whenitappears,stateofFlip-Flopscanchangeinto“000”atnegativeedge,sowecalledsystemofthiskind“self-startup”system.DigitalLogic27Example3(Insteps)4,DrawtheconclusionaboutthecircuitModulo-7SynchronousUpCounter(同步模7加法計數(shù)器)000001010011100101110111Someterms:Synchronous/Asynchronous;

Up/Down/Up-down/Bi-directional;

DigitalLogic28StepsofDesign/SynthesisofSequentialCircuitsGivenSpecifi-cationOfCircuitsResultCircuitsDerivetheOriginalStateTableOutputEquation&DrivingEquationThat’swhatwehaveThis’sourtargetHowmanystatesshouldtherebeinallweneedittobuildcircuitsDerivetheReducedStateTable(Optional)EncodeTheStatesCheckSelf-StartupHerecomedifficultiesCancauseRedesignDigitalLogic29Example1(Design)(Indetail)1,Generatetheoriginalstatetable(原始狀態(tài)表)DesignaModulo-7BinarySynchronousUpCounter(Mooretype),therulesincludethat

itshouldgenerateanoutput“1”whilecarrybitappears.2,Converttothereducedstatetable:Thatisthemostreducedone.3,Encodestatesandselectproperflip-flops狀態(tài)已經(jīng)對應(yīng)于編碼,故無須重編(此類應(yīng)用的共性)NumberofStatesis7,soweneed3FFs.SelectJKFFasaninstanceState:000=>001=>010=>011=>100=>101=>110=>000Y:0000001DigitalLogic30Example1(Indetail)4,Derivetheoutputequation,stateequations&Drivingequations001000d00001111001YQn(2,1,0)Qn+1(2,1,0)Y0000010001010001001100111000100101010111001100001111dddd/1DigitalLogic31Example1(Indetail)000101d10001111001Q2(n+1)Qn(2,1,0)Qn+1(2,1,0)Y0000010001010001001100111000100101010111001100001111d/0ddd/14,Derivetheoutputequation,stateequations&DrivingequationsDigitalLogic32Example1(Indetail)0001111001Q2(n+1)000101d14,Derivetheoutputequation,stateequations&DrivingequationsDigitalLogic33Example1(Indetail)4,Derivetheoutputequation,stateequations&Drivingequations0001111001Q2(n+1)000101d1DigitalLogic34Example1(Indetail)010010d10001111001Q1(n+1)Qn(2,1,0)Qn+1(2,1,0)Y0000010001010001001100111000100101010111001100001111d/0d/0dd/14,Derivetheoutputequation,stateequations&DrivingequationsDigitalLogic35Example1(Indetail)110100d00001111001Q0(n+1)Qn(2,1,0)Qn+1(2,1,0)Y0000010001010001001100111000100101010111001100001111d/0d/0d/0d/14,Derivetheoutputequation,stateequations&DrivingequationsDigitalLogic36Example1(Indetail)110100d00001111001Q0(n+1)上式不滿足JK方程雛形形式,但是其不滿足之處僅僅表現(xiàn)為缺少對應(yīng)的項:Q0n,對于這種“缺項”形式,我們可以方便地將其構(gòu)造出來.方式是:+0構(gòu)造.在本例中,如果將d看作1,也可以構(gòu)造出Q0n,但是卻犧牲了電路的簡潔性.4,Derivetheoutputequation,stateequations&DrivingequationsDigitalLogic37Example1(Indetail)Herecomesthedifficultpoint,whiledevelopingdesign,weshouldconverttheresultstateequationintospecialformwhichlookslikeFF’scharacteristicequation.Meanwhile,wecansee,forsystemswithunspecifiedstatetable,theresultfunctionmaybevarious.Thecorrectanswermaynotbeunique.5,Checkifsystemcanself-startupTheanswerisqualifiedYES.4,Derivetheoutputequation,stateequations&Drivingequations一個可行的方法是將非完全確定次態(tài)強(qiáng)行指定為有效狀態(tài)。其帶來的后果是電路可能非最簡。DigitalLogic38Example1(Indetail)6,DrawthecircuitdiagramDigitalLogic39Example1(Indetail)7,Sth.shouldbementionedQuestion:Isthereanythingfaulty(缺陷之處)?Answer:Whensystemstatechangesfrom“111”

to“000”,itwillgenerateanunexpectedoutput(錯誤輸出)Y=1.Wecancorrectthissystembymodifyingthecircuits.NewK-Mapisasfollowing:0d=00001000001111001YDigitalLogic40Example1(Indetail)7,Sth.shouldbementionedQuestion:AtP37,canwedetermine‘d’tobe1or0randomly(任意)?Whatshouldwetakeintoaccount(考慮到)

whiledoingthis?Answer:weshouldconsiderthefunctionofself-startup,foritisdeterminedcompletelybythenextstateofinvalidstate.DigitalLogic41Example1(Indetail)7,Sth.shouldbementionedResultofthisexampleExample3(analysis)Question:Aretheydestinedto(注定會)bethesame?DigitalLogic42Example2(Design)(Insteps)1,Draworiginalstatediagram(原始狀態(tài)圖)Designcircuitswithsuchrules:whichreceive3-bitserialinputandgenerateanoutputwiththeseprinciples(odd-evencheck):

ifthenumberof‘1’iseven,theoutputis1,otherwiseitis0.Every3bitsmakeupagroupandafterreceiving3bits,circuitsreturnbacktotheinitializedstate.A0/01/0BCEDFG0/01/00/01/00/11/00/01/10/01/10/11/0DigitalLogic43Example2(Insteps)1,Generateoriginalstatetable(原始狀態(tài)表)Asinlefttable,thereareredundantstates:D=G,

E=F;Thephysicalmeaning(物理意義)ofequation“D=G”

is:Ifcircuitreceivesserial“00”(A->B->D),oritreceives“11”(A->C->G),theeffectsarethesame;當(dāng)然，并非只有完全相等的兩組狀態(tài)才是等價的(存在多種可能).PresentStateNextState/OutputX=0X=1AB/0C/0BD/0E/0CF/0G/0DA/1A/0EA/0A/1FA/0A/1GA/1A/0DigitalLogic44Example2(Insteps)2,ReducedstatetablePresentStateNextState/OutputX=0X=1AB/0C/0BD/0E/0CE/0D/0DA/1A/0EA/0A/1DigitalLogic45Example2(Insteps)3,Encodestates,

theprinciplesofencodingare:Withsamenextstate,theircodesshouldbeneighbor;Nextstatesofonestateshouldbeneighbor;Withsameoutput,theircodesshouldbeneighbor;Themostfrequentstateintableshouldbelogic0.Q3Q2Q10001111001EDCBANumberofstatesis5,soweneed3Flip-Flops.Theresultisasinright

table:對狀態(tài)的編碼分配沒有錯對之分,只有優(yōu)劣之別.會影響所設(shè)計電路的復(fù)雜程度.DigitalLogic46Example2(Insteps)4,StateTransitionDiagram:A0/01/0BCEDFG0/01/00/01/00/11/00/01/10/01/10/11/0A0/01/0BCED0/01/01/00/00/11/00/01/1ReduceDigitalLogic47Example2(Insteps)4,StateTransitionTable:

Q3Q2Q10001111001EDCBAPresentState(Q3Q2Q1)NextState(Q3Q2Q1)/ZX=0X=1000010/0110/0001ddd/dddd/d010100/0101/0011ddd/dddd/d100000/1000/0101000/0000/1110101/0100/0111ddd/dddd/dA0/01/0BCED0/01/01/00/00/11/00/01/1DigitalLogic48Example2(Insteps)4,FromSTTtoK-Map:PresentState(Q3Q2Q1)NextState(Q3Q2Q1)/ZX=0X=1000010/0110/0001ddd/dddd/d010100/0101/0011ddd/dddd/d100000/1000/0101000/0000/1110101/0100/0111ddd/dddd/dZxQ3Q2Q1

000111100001111001