著名半導(dǎo)體公司DFTATPG內(nèi)部培訓(xùn)資料課件

ATPGIntroductionforIPTeam

AgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhat’sit?DFTStructuredDFTATPGTerminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageAgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhat’sit?DFTStructuredDFTATPGTerminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageWhat’sDFTDFT(DesignForTest)Testabilityisadesignattributethatmeasureshoweasyitistocreateaprogramtocomprehensivelytestamanufactureddesign’squality.Traditionally,designandtestprocesseswerekeptseparate,withtestconsideredonlyattheendofthedesigncycle.Butincontemporarydesignflows,testmergeswithdesignmuchearlierintheprocess,creatingwhatiscalledadesign-for-test(DFT)processflow.Testablecircuitryisbothcontrollableandobservable.Inatestabledesign;settingspecificvaluesontheprimaryinputsresultsinvaluesontheprimaryoutputswhichindicatewhetherornottheinternalcircuitryworksproperly.Toensuremaximumdesigntestability,designersmustemployspecialDFTtechniquesatspecificstagesinthedevelopmentprocess.What’sStructuredDFT?StructuredDFTProvidessystematicandautomaticapproachtoenhancingdesigntestability.Goalistoincreasethecontrollabilityandobservabilityofacircuit.Methods:scandesigntechnique,whichmodifiestheinternalsequentialcircuitryofthedesign.Built-inSelf-Test(BIST)method,whichinsertsadevice’stestingfunctionwithinthedeviceitself.boundaryscan,whichincreasesboardtestabilitybyaddingcircuitrytoachip.What’sATPGATPG(AutomaticTestPatternGeneration)Testpatterns(testvectors),aresetsof1sand0splacedonprimaryinputpinsduringthemanufacturingtestprocesstodetermineifthechipisfunctioningproperly.ATE(AutomaticTestEquipment)determinesifthecircuitisfreefrommanufacturingdefectsbycomparingthefault-freeoutput—whichisalsocontainedinthetestpattern—withtheactualoutputmeasuredbytheATE.Goal:createasetofpatternsthatachievesagiventestcoverage.ThenrunitonTester.Passindicatednorelateddefectsexistinthischip.SCANCell/SCANChainScanCellInnormaloperation(sc_en=0),systemdatapassesthroughthemultiplexertotheDinputoftheflip-flop,andthentotheoutputQ.Inscanmode(sc_en=1),scaninputdata(sc_in)passestotheflip-flop,andthentothescanoutput(sc_out).ScanChainAsetofseriallylinkedscancells.Eachscanchaincontainsanexternalinputpinandanexternaloutputpinthatprovideaccesstothescancells.Thescanchainlength(N)isthenumberofscancellswithinthescanchain.SCANProcedureTheoperatingprocedureofthescancircuitryisasfollows:1.Enablethescanoperationtoallowshifting(toinitializescancells).2.Afterloadingthescancells,holdthescanclocksoffandthenapplystimulustotheprimaryinputs.3.Measuretheoutputs.4.Pulsetheclocktocapturenewvaluesintoscancells.5.Enablethescanoperationtounloadandmeasurethecapturedvalueswhilesimultaneouslyloadinginnewvaluesviatheshiftingprocedure(asinstep1).BeforeScanAfterScanSCANWaveformscan_clkscan_seLoadshiftshiftshiftLoad/UnloadshiftshiftshiftcapturecaptureLoad/UnloadcaptureLoad/UnloadcaptureUnloadStuck-AtFaultModelExample:SingleStuck-AtFaultsforANDGateThesinglestuck-atmodelisthemostcommonfaultmodelusedinfaultsimulation,becauseofitseffectivenessinfindingmanycommondefecttypes.Thestuck-atfaultmodelsthebehaviorthatoccursiftheterminalsofagatearestuckateitherahigh(stuckat-1)orlow(stuck-at-0)voltage.Thefaultsitesforthisfaultmodelincludethepinsofprimitiveinstances.Alls-a-0faultsintheANDgateareequivalents-a-1s-a-0s-a-1s-a-0s-a-1s-a-0s-a-0s-a-0s-a-1s-a-1s-a-0s-a-1PossibleErrors:6PossibleErrors:4Stuck-AtCoverageReport

#DT--------------------------------------TestCoverage=#FU-#UU-#TI-#BL-#RE#DT--------------------------------------FaultCoverage=#FUStatisticsreport------------------------------------------- #faults #faultsfaultclass (coll.) (total)------------------------------ -------FU(full)1171003 1824936------------------------------ -------UC(uncontrolled) 32 84UO(unobserved)946 1286DS(det_simulation)3580 8011DI(det_implication)4 10(protected)1138170 1767804PU(posdet_untestable)784 1806PT(posdet_testable)34 42UU(unused)3035 5344TI(tied)2093 2201BL(blocked)331 333RE(redundant)8272 10462AU(atpg_untestable)13722 27553------------------------------ -------test_coverage98.66% 98.30%fault_coverage97.50% 97.31%atpg_effectiveness99.91% 99.92%------------------------------ -------ProtectedFaultsalone:test_coverage98.35% 97.85%fault_coverage97.20% 96.87%-------------------------------------------#test_patterns 271#simulated_patterns 271CPU_time(secs) 18364.6-------------------------------------------

AgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhat’sit?DFTStructuredDFTATPGTerminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageDividedClockSomedesignscontainuncontrollableclockcircuitry;thatis,internally-generatedsignalsthatcanclock,set,orresetflip-flops.Ifthesesignalsremainuncontrollable,theycoulddisturbsequentialelementsduringscanshifting.Thus,thesystemcannotconverttheseelementstoscan.new_clk=scan_mode?tst_clk:gen_clkAsyncResetTestLogicAddedtoControlAsynchronousResetuseipt_async_setocontrolthemux.new_rst=ipt_se_async_xxx?ext_rst:int_rstAsyncReset(2)Forthecasewherebothsetandresetofaflopareinternallygenerated,eithersetorresetshallbedisabledduringscanmodeusing"ipt_mode_scan"signal,whileothercanbemuxedwithhardresetusing"ipt_se_async"signal.Selectionofdisablingset/resetsignalshallbedecidedhavinglesscombinationallogicforgettingbettertestcoverage.ClockGating(2)ClockGatingCellCPE+TEQDQAgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhat’sit?DFTStructuredDFTATPGTerminologyinScanScance