電子科技大學-數(shù)字電路基礎-Chapter 3-1 Digital Circuits

Chapter3

DigitalCircuitsAbinarynumbersystemcontainstwosymbolsandasetofoperationsButwhatdoesa'0'ora'1'looklikeinreallife?Manythingscanrepresents0'sand1's,butweareinterestedinrepresentingthemusing"electricalsignals"Then,howtorepresenta0or1withanelectricalsignal(voltageorcurrent)?Weneedtoknowtheknowledgeoftheelectricalaspectsofdigitalcircuits.3.1LogicSignalsandGatesLogicSignals

-alogicsignalmaylooklikethis…tv(t)vthresholdwedefineathresholdtorepresentwhenweconsiderthesignalaLOGIC0orLOGIC1.Digitaldesignersoftenusethewords“LOW”and“HIGH”inplaceof“0”and“1”.LogicSignalsandGatesHowtogettheHIGHandLOWVoltage？AssignHIGHto0or1？VOUTVINVccR獲得高、低電平的基本原理PositiveLogic(正邏輯)10NegativeLogic(負邏輯)10LogicSignalsandGatesLogicCircuit

-acircuitthatproduceslogicoutputsdependingonthelogicinputs

ex)LogicWeneedtoknow-theelectricalbehaviorofthecircuit-thelogicrelationbetweeninputsandoutputsBasicConceptsTwotypesoflogiccircuits：Combinationallogiccircuit（組合邏輯電路）Sequentiallogiccircuit（時序邏輯電路）AlogiccircuitwhoseoutputsdependonlyonitscurrentinputsAlogiccircuitwithmemory,whoseoutputsdependonthecurrentinputsandthesequenceofpastinputsBasiclogicfunctions:AND,OR,NOTBasicLogicFunction:AND000010100111ABZLogicExpression(邏輯表達式)Z=A·BSwitch:1-on,0-offLamp:1-Light,0-outProducea1outputifandonlyifallofitsinputsare1TruthTable

(真值表)&ABZABZ（邏輯符號）ABZLogicSymbolBasicLogicFunction:ORLogicExpressionZ=A+BABZABZProducea1ifandonlyifoneormoreofitsinputare1

≥1ABZABZ000011101111TruthTableLogicSymbolAZ0110LogicExpressionY=A=A’AZRProduceanoutputvaluethatistheoppositeofitsinputvalue.UsuallycalledanInverter

（反相器）1ZAAZBasicLogicFunction:NOTTruthTableLogicSymbolNANDandNORNAND(與非)

LogicExpressionZ=(A·B)’

LogicSymbolNOR(或非)

LogicExpressionZ=(A+B)’

LogicSymbol

&≥1TruthTable&≥1Operation

NAND

NOR

Symbol

ExpressionY=(A?B)’Y=(A+B)’AB

0

0

1

11

Y

1

1

1

0

Y

1

0

0

0

100ComplexLogicfunctionAND-OR-INVERT

(與或非）ABCD&≥1YABYCDF=(AB+CD)’XORandXNORXOR(ExclusiveOR,異或)2-inputgatewhoseoutputis1iftheinputsaredifferent.XNOR(ExclusiveNOR,同或)

2-inputgatewhoseoutputis1iftheinputsaresame.F=AB=A’·B+A·B’F=A⊙B=A·B+A’·B’ABF000011101110XORABF001010100111XNORAB=(A⊙B)’OperationXORXNOR

Symbols

ExpressionY=AB

=AB+ABY=A⊙B=AB+ABAB

0

0

0

1

1

0

11

Y

0

1

1

0

Y

1

0

0

1

=1ABYABYABY=ABYTruthtableAB=A⊙BA⊙B=AB3.2LogicFamiliesLogicGates

-we'veseenthebasiclogicgatesthatweusetoformmorecomplexlogicexpressions

INV,AND,NAND,OR,NOR,XOR,XNORLogicSignaling

-we'veseenhowweuseanelectricalsignaltorepresentandtransmitlogicvaluestAB10101011113.2LogicFamiliesNowwewanttoseehowweactuallycreatethesecircuitsandsignalsusingelectronicsTherearedifferentways(orcircuits)toimplementlogicgatesThecircuitsaredesignedtointerfacewithothercircuitswiththesametypeofdesignAcollectionofIC'sdesignedtointerfacewitheachotheriscalleda"LogicFamily"Themostcommonfamilieswedealwithare:

1)CMOS 2)TTL3.3CMOSLogicCMOSLogiclevels5.0V3.5V1.5V0.0VATypicalLogicCircuit:5-VoltPowerSupplyOtherPower-SupplyVoltages:3.3,2.5or1.8VoltsLogic1(High)Logic0(Low)undefinedMOSFET(MOS晶體管)twotypesofMOSFET's:NMOS,PMOSDrain(漏極)Source(源極)Gate(柵極)Vgs+NMOSSource(源極)Drain(漏極)Gate(柵極)

+VgsPMOS-thesedevicecanbethoughtofasa"voltagecontrolledresistor"-alterthevoltageontheGatetoturnON/OFFthecurrentflowMOSFET(MOS晶體管)twotypesofMOSFET's:NMOS,PMOSDrain(漏極)Source(源極)Gate(柵極)Vgs+NMOSUsually：Vgs>=0

Vgs=0Rds

VeryHigh

OFF(截止狀態(tài))

VgsRds

ON(導通狀態(tài))MOSFET(MOS晶體管)twotypesofMOSFET's:NMOS,PMOS：Source(源極)Drain(漏極)Gate(柵極)

+VgsPMOSUsually：Vgs<=0

Vgs=0RdsVeryHigh

Off(截止狀態(tài))

Vgs

Rds

On(導通狀態(tài))MOSFET(MOS晶體管)ThegateofaMOStransistorhasaveryhighimpedance.（overamegohm,大于兆歐）Regardlessofgatevoltage,almostnocurrentbetweengate-sourceorgate-drain （漏電流leakagecurrent,microampereA）ThegateofaMOStransistoriscapacitivelycoupledtothesourceanddrain.

柵極與源和漏極之間有電容耦合。輸入信號轉換時，電容充放電，功耗較大BasicswitchingcircuitofMOSFETvI+–vO–+iD+VDDRDDGSChoosingproperparameters,LOWInput,OFF,HIGHOutputHIGHInput,ON,LOWOutputBasicCMOSInverterCircuitFunctionalBehavior1、VIN=0.0V VGSN=0.0V，TnOFF VGSP=VIN–VDD=–5.0V，TpON

VOUT

VDD=5.0V2、VIN=VDD=5.0V VGSN=5.0V，TnON VGSP=VIN–VDD=0.0V，TpOFF VOUT

0VDD=+5.0VVOUTVINTpTnGDSSBasicCMOSInverterCircuitVDD=+5.0VVOUTVINTpTnGDSSVDDVINVOUTOnwhenVINislowOnwhenVINishigh(p-channel)(n-channel)CMOSNANDGate

FunctionalBehavior1、EitherInput(AorB)isLow,Then EitherT1,T3isOff EitherT2,T4isOn ZisHigh[ZVDD]2、BothInputs(AandB)areHigh,Then BothT1,T3areOn BothT2,T4areOff ZisLow[Z0V]VDD=+5.0VZABT1T2T4T3CMOSNORGateFunctionalBehavior

1、BothInputs(AandB)areLow,Then BothT1,T3areOff BothT2,T4areOn ZisHigh[ZVDD]2、EitherInput(AorB)isHigh,Then EitherT1,T3isOn EitherT2,T4isOff ZisLow[Z0V]VDD=+5.0VZABT1T2T4T3CMOS

NANDandNORgatesdonothaveidenticalelectricalperformance.Foragivensiliconarea,ann-channeltransistorhaslower“on”resistancethanap-channeltransistor.Therefore,whentransistorsareputinseries,k

n-channeltransistorshavelower“on”resistancethandok

p-channelones.Whoisfaster,k-inputNANDork-inputNORgate?k-inputNANDisfaster,morepopular.Fan-In（扇入）Fan-In,theNumberofInputsthataGatecanhave.TheAdditive“on”ResistanceofseriestransistorslimitstheFan-InofCMOSgates. (導通電阻的可加性限制了CMOS門的扇入數(shù))WhoseFan-Inislarger,NANDorNOR?Typically,Fan-Inis4forNORgatesand6forNANDgates.Fan-In（扇入）AlargenumberofinputscanbemadebycascadinggateswithfewerinputsF=ABCDEFGHNon-invertingGatesVDD=+5.0VAZ(Non-invertingbuffers)非反相緩沖器HowtogetaANDGate?VDD=+5.0VABZCDCMOSAND-OR-INVERTGate

Z=AB+CDCABBADCDX=(A+B)?(C+D)DABCDABCOUT=D+A?(B+C)Challenge:??3.4ElectronicBehaviorofCMOSCircuitsLogicVoltageLevels(邏輯電壓電平)DCNoiseMargins

(直流噪聲容限)Fan-Out(扇出)Speed,PowerConsumption

(速度、功耗)Noise,ElectrostaticDischarge

(噪聲、靜電放電)Open-DrainOutputs,ThreeStateOutputs(漏極開路輸出、三態(tài)輸出)ElectricalNotlogic（Table3-3）DataSheet（數(shù)據(jù)表）Specifications(規(guī)格說明)3.5CMOSStaticElectricalBehaviorCMOSStaticBehavior

-"Static"or"DC"referstothegate'soperationwhentheinputsareNOTchanging

-alsocalled"SteadyState”CMOSDynamicBehavior

-Alsocalled"AC"performance3.5.1LogicLevelsandNoiseMarginsLogicLevelsandNoiseMarginsVOUTVIN5.01.53.55.0Typicalinput-outputtransfercharacteristicofaCMOSinverterVDD=+5.0VVOUTVINTpTn0101LogicLevelsSpecificationsHIGHABNOMALLOWVOLmaxVILmaxVIHminVOHminVCC－0.1Vground＋0.1V0.7VCC0.3VCC3.5.1LogicLevelsandNoiseMarginsDCNoiseMargin(多大的噪聲會使最壞輸出電壓被破壞得不可識別)3.5.1LogicLevelsandNoiseMarginsVDDVoutHIGHVOHminVSSLOWVOLmaxVDDHIGHVIHminVSSLOWVILmaxVinNoiseMarginNoiseMarginHIGHStateNoiseMargin:(VOHmin-VIHmin)

LOWStateNoiseMargin:(VILmax-VOLmax)LeakageCurrentRegardlessofthevoltageappliedtotheinputofaCMOSdevice,theinputconsumesverylittlecurrent.Onlytheleakagecurrentofthetransistors’gates.thereisaspecificationthattellsushowmuchcurrentcanbeexpectedtoflow--IIH

:MaximumcurrentflowingwhendrivingaHIGH--IIL

:MaximumcurrentflowingwhendrivingaLOW3.5.1LogicLevelsandNoiseMargins3.5.2CircuitBehaviorwithResistiveLoadsVCCAZVCCRThevRpRnVThev

+VOUTVINResistiveLoads

-RequirenontrivialamountsofcurrenttooperateCMOSDrivingaLOWVOUT<=VOLmaxTheOutputsinkCurrent－Sinkingcurrent(吸收電流或灌電流）

IOLmax:MaximumcurrentthatcanbesinkedwhendrivingaLOW3.5.2CircuitBehaviorwithResistiveLoadsVCC=+5.0VRp>1MRnResistiveLoadsVOLmaxIOLmaxCMOSDrivingaHIGHVOUT>=VOHminTheOutputsourceCurrent－Sourcingcurrent(提供電流或拉電流）

IOHmax:MaximumcurrentthatcanbesourcedwhendrivingaHIGH3.5.2CircuitBehaviorwithResistiveLoadsVCC=+5.0VRpRn>1MResistiveLoadsVOHminIOHmax3.5.2CircuitBehaviorwithResistiveLoadsVOUT=0VCC=+5.0VRThevVThev

+VIN=1CMOSDrivingaLOWEstimatetheSinkingcurrent3.5.2CircuitBehaviorwithResistiveLoadsVCC=+5.0VRThevVThev

+VOUT=1VIN=0CMOSDrivingaHIGHEstimatetheSourcecurrent：3.5.3CircuitBehaviorwithNon-idealInputsSofar,wehaveassumedthattheHIGHandLOWinputstoaCMOScircuitareidealvoltages,veryclosetothepower-supplyrails.Iftheinputvoltageisnotclosetothepower-supplyrail-The“ON”transistormaynotbefully“ON”-The“OFF”transistormaynotbefully“OFF”Thesetwoeffectscombinetomovetheoutputvoltageawayformthepower-supplyrail.3.5.3CircuitBehaviorwithNon-idealInputsVCC=+5.0V4002.5kVIN1.5VVOUT4.31VVCC=+5.0V4k200VIN3.5VVOUT0.24V輸出電壓變壞（有電阻性負載時更差）更糟糕的是：輸出端電流，功耗3.5.4Fan-outFan-Out: -TheNumberofInputsthatthegatecandrivewithoutexceedingitsworst-caseloadingspecifications.Fan-outmustbeexaminedforbothpossibleoutputstates,HIGNandLOWOverallFan-out=Min(HIGH-stateandLOW-state)

【總扇出＝min（高態(tài)扇出，低態(tài)扇出）】DCFan-outandACFan-out

(直流扇出和交流扇出)74HCTDrives74LSLOWFan-Out

(低態(tài)扇出):Fan-OUT

HIGHFan-Out(高態(tài)扇出)：“excess”drivingcapability:(高態(tài)剩余驅動能力)CMOS