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ADIADSP-BF609Blackfin處理器高清視頻開發(fā)方案關(guān)鍵字:工業(yè)控制,儀器儀表,馬達控制;汽車電子ADI公司的ADSP-BF609是Blackfin雙核處理器,工作頻率高達1GHz,硬件支持高清視頻分析.ADSP-BF609采用ADI/INTEL微信號架構(gòu)(MSA),每個核包含兩個16位MAC,兩個40位ALU和40位桶形移位RISC類寄存器和指令模式,具有先進的調(diào)試,跟蹤和性能監(jiān)視,主要用在從汽車電子到嵌入式工業(yè),儀表和馬達控制等應用.本文介紹了ADSP-BF609主要特性,方框圖,Blackfin處理器核框圖以及ADSP-BF609EZ-KITLite?評估系統(tǒng)主要特性,框圖,電路圖和材料清單.ADI
TheADSP-BF609processorisamemberoftheBlackfinfamilyofproducts,incorporatingtheAnalogDevices/IntelMicroSignalArchitecture(MSA).Blackfinprocessorscombineadual-MACstate-of-the-artsignalprocessingengine,theadvantagesofaclean,orthogonalRISC-likemicroprocessorinstructionset,andsingle-instruction,multiple-data(SIMD)multimediacapabilitiesintoasingleinstruction-setarchitecture.
Theprocessoroffersperformanceupto500MHz,aswellaslowstaticpowerconsumption.Producedwithalow-powerandlowvoltagedesignmethodology,theyprovideworld-classpowermanagementandperformance.
Byintegratingarichsetofindustry-leadingsystemperipheralsandmemory,Blackfinprocessorsaretheplatformofchoicefornext-generationapplicationsthatrequireRISC-likeprogrammability,multimediasupport,andleadingedgesignalprocessinginoneintegratedpackage.Theseapplicationsspanawidearrayofmarkets,fromautomotivesystemstoembeddedindustrial,instrumentationandpower/motorcontrolapplications.
ADSP-BF609主要特性:
Dual-coresymmetrichigh-performanceBlackfinprocessor,upto500MHzpercoreEachcorecontainstwo16-bitMACs,two40-bitALUs,anda40-bitbarrelshifter
RISC-likeregisterandinstructionmodelforeaseofprogrammingandcompiler-friendlysupport
Advanceddebug,trace,andperformancemonitoring
PipelinedVisionProcessorprovideshardwaretoprocesssignalandimagealgorithmsusedforpre-andco-processingofvideoframesinADASorothervideoprocessingapplications
AcceptsarangeofsupplyvoltagesforI/Ooperation.
Off-chipvoltageregulatorinterface349-ball(19mm×19mm)RoHScompliantBGApackage
MEMORY
Eachcorecontains148KbytesofL1SRAMmemory(processorcore-accessible)withmulti-paritybitprotection
Upto256KbytesofL2SRAMmemorywithECCprotection
Dynamicmemorycontrollerprovides16-bitinterfacetoasinglebankofDDR2orLPDDRDRAMdevices
Staticmemorycontrollerwithasynchronousmemoryinterfacethatsupports8-bitand16-bitmemories
Flexiblebootingoptionsfromflash,eMMCandSPImemoriesandfromSPI,linkportandUARThosts
Memorymanagementunitprovidesmemoryprotection
圖1.ADSP-BF609處理器方框圖
BLACKFIN處理器核
TheprocessorintegratestwoBlackfinprocessorcores.Eachcorecontainstwo16-bitmultipliers,two40-bitaccumulators,two40-bitALUs,fourvideoALUs,anda40-bitshifter.Thecomputationunitsprocess8-,16-,or32-bitdatafromtheregisterfile.
Thecomputeregisterfilecontainseight32-bitregisters.Whenperformingcomputeoperationson16-bitoperanddata,theregisterfileoperatesas16independent16-bitregisters.Alloperandsforcomputeoperationscomefromthemultiportedregisterfileandinstructionconstantfields.
EachMACcanperforma16-bitby16-bitmultiplyineachcycle,accumulatingtheresultsintothe40-bitaccumulators.Signedandunsignedformats,rounding,andsaturationaresupported.
TheALUsperformatraditionalsetofarithmeticandlogicaloperationson16-bitor32-bitdata.Inaddition,manyspecialinstructionsareincludedtoacceleratevarioussignalprocessingtasks.Theseincludebitoperationssuchasfieldextractandpopulationcount,modulo232multiply,divideprimitives,saturationandrounding,andsign/exponentdetection.Thesetofvideoinstructionsincludebytealignmentandpackingoperations,16-bitand8-bitaddswithclipping,8-bitaverageoperations,and8-bitsubtract/absolutevalue/accumulate(SAA)operations.
Alsoprovidedarethecompare/selectandvectorsearchinstructions.Forcertaininstructions,two16-bitALUoperationscanbeperformedsimultaneouslyonregisterpairs(a16-bithighhalfand16-bitlowhalfofacomputeregister).IfthesecondALUisused,quad16-bitoperationsarepossible.
The40-bitshiftercanperformshiftsandrotatesandisusedtosupportnormalization,fieldextract,andfielddepositinstructions.
Theprogramsequencercontrolstheflowofinstructionexecution,includinginstructionalignmentanddecoding.Forprogramflowcontrol,thesequencersupportsPCrelativeandindirectconditionaljumps(withstaticbranchprediction),andsubroutinecalls.Hardwaresupportszero-overheadlooping.
Thearchitectureisfullyinterlocked,meaningthattheprogrammerneednotmanagethepipelinewhenexecutinginstructionswithdatadependencies.
Theaddressarithmeticunitprovidestwoaddressesforsimultaneousdualfetchesfrommemory.Itcontainsamultiportedregisterfileconsistingoffoursetsof32-bitindex,modify,length,andbaseregisters(forcircularbuffering),andeightadditional32-bitpointerregisters(forC-styleindexedstackmanipulation).
BlackfinprocessorssupportamodifiedHarvardarchitectureincombinationwithahierarchicalmemorystructure.Level1(L1)memoriesarethosethattypicallyoperateatthefullprocessorspeedwithlittleornolatency.AttheL1level,theinstructionmemoryholdsinstructionsonly.Thedatamemoryholdsdata,andadedicatedscratchpaddatamemorystoresstackandlocalvariableinformation.
Inaddition,multipleL1memoryblocksareprovided,offeringaconfigurablemixofSRAMandcache.Thememorymanagementunit(MMU)providesmemoryprotectionforindividualtasksthatmaybeoperatingonthecoreandcanprotectsystemregistersfromunintendedaccess.
Thearchitectureprovidesthreemodesofoperation:usermode,supervisormode,andemulationmode.Usermodehasrestrictedaccesstocertainsystemresources,thusprovidingaprotectedsoftwareenvironment,whilesupervisormodehasunrestrictedaccesstothesystemandcoreresources.
圖2.Blackfin處理器核框圖
ADSP-BF609EZ-KITLite?評估系統(tǒng)
TheADSP-BF609processorisamemberoftheBlackfinfamilyofproducts,incorporatingtheAnalogDevices/IntelMicroSignalArchitecture(MSA).Blackfinprocessorscombineadual-MACstate-of-the-artsignalprocessingengine,theadvantagesofaclean,orthogonalRISC-likemicroprocessorinstructionset,andsingle-instruction,multiple-data(SIMD)multimediacapabilitiesintoasingleinstruction-setarchitecture.
ADSP-BF60xBlackfinprocessorsembodyanewtypeofembeddedprocessordesignedspecificallytomeetthecomputationaldemandsandpowerconstraintsoftoday’sautomotivesystems,embeddedindustrial,instrumentation,andpower/motorcontrolapplications.
TheevaluationboardisdesignedtobeusedinconjunctionwiththeCrossCore?EmbeddedStudio(CCES)developmenttoolstotestcapabilitiesoftheADSP-BF60xBlackfinprocessors.TheCCESdevelopmentenvironmentaidsadvancedapplicationcodedevelopmentanddebug,suchas:
?Create,compile,assemble,andlinkapplicationprogramswritteninC++,C,andassembly
?Load,run,step,halt,andsetbreakpointsinapplicationprograms
?Readandwritedataandprogrammemory
?Readandwritecoreandperipheralregisters
?Plotmemory
Accesstotheprocessorfromapersonalcomputer(PC)isachievedthroughaUSBport(whenadebugagentismountedontheEZ-KITLiteboard)oranexternalJTAGemulator.TheUSBinterfaceprovidesunrestrictedaccesstotheADSP-BF609processorandevaluationboardperipherals.AnalogDevicesJTAGemulatorsofferfastercommunicationbetweenthehostPCandtargethardware.AnalogDevicescarriesawiderangeofin-circuitemulationproducts.
圖3.ADSP-BF609EZ-KITLite?評估板外形圖
ADSP-BF609EZ-KITLite?評估板主要特性:
?AnalogDevicesADSP-BF609Blackfinprocessor
?349-pinLFBGApackage
?25MHzCLKINoscillator
?48MHzUSBCLKIN
?DoubleDataRateSynchronousDynamicRandom-AccessMemory(DDR2SDRAM)
?MicronMT47H64M16HR-3
?64Mx16bit(1Gb)
?Burstflashmemory
?MicronPC28F128P33T85B
?16Mx16-bit(32MB)flashmemory
?QuadSerialPeripheralInterface(SPI)
?WinbondW25Q32
?32Mbserialflashmemory
?EthernetPHY
?NationalSemiconductor
?DP83848C10/100PHY
?TwoLEDsintegratedintotheRJ-45connector:link/activity
?UniversalAsynchronousReceiver/Transmitter(UART)
?ADM3315RS-232linedriver/receiver
?DB9femaleconnector
?Tempsensor
?OnSemiconductor
?ADM1032two-wiresensor
?ControllerAreaNetwork(CAN)
?NXPTJA1041
?RJ-11connector
?Debuginterface
?JTAGheaderforusewithADIemulators
?Standalonedebugagent
?LEDs
?EightLEDs:onepower(green),oneboardreset(red),onetemperaturelimit(amber),Ethernetspeed(green),andfourgeneral-purpose(amber)
?Pushbuttons
?Fourpushbuttons:onereset,onewake,andtwoIRQ/flag
?ExpansionInterface3(EI3)
?Nextgenerationoftheexpansioninterfacedesign,providesaccesstomostoftheprocessorsignals
?Powersupply
?CEapproved
?5V@3.6Amps
?Otherfeatures
?Linkportconnectors
?SD/MMCmemoryconnector
?Rotaryencoder
?MPJTAGinandoutconnectors
?0.05-ohmresistorsforprocessorcurrentmeasurem
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