單周期控制航空航天計(jì)算機(jī)學(xué)院

航空航天大學(xué)計(jì)算機(jī)學(xué)院航空航天大學(xué)計(jì)算機(jī)學(xué)院CS617的21MachineMachineLanguageProgram(MIPS)GreatIdea#1:Levelsoftemp=v[k];v[k]=v[k+1];v[k+1]=temp;lw$t0,0($2)lw$t1,4($2)sw$t1,0($2)sw$t0,0000100111000110101011110101101011110101100000001001110011000110101011110101100000000101100000001001110001101010(e.g.blockdiagrams)LogicCircuitDescription(CircuitSchematicDiagrams)Weare Summer2012‐‐Lecture AssemblyLanguageProgram(e.g.Program(e.g.C)HardwareHardwareDesignrecodersmultiplexer Summer2012‐‐Lecture4CS617的21DatapathDatapathPartoftheprocessor;thehardwarenecessarytoperformalloperationsrequiredDependsonexactISA,RTLofMajorPCandRegisterFile(RegFileholdsInstructionandDataALUforoperations(ontwoExtender(sign/zeroSummer2012‐‐Lecture6FiveStagesoftheFiveStagesofthe2. 3.Execute4.Memory5. Summer2012‐‐Lecture7DatapathDatapathandRoutepartsofdatapathbasedonISAAddMUXestoselectfrommultipleAddcontrolsignalsforcomponentinputsandHowwidedoeseachoneneedtoForeachinstruction,assignappropriatevalueforcorrectroutingSummer2012‐‐Lecture8MIPS‐liteInstruction40MIPS‐liteInstruction401InstrFetchSummer2012‐‐Lecture9MIPS‐liteDatapathControl0→“zero”;1→“sign”?MemWr: 1→writememory0→busB;1→imm16 ?MemtoReg:01→Mem“ADD”,“SUB”,“OR”0→+4;1→RegDstrd0→“rt”;1→10 RWRA=0032WrEn1Data1 Summer2012‐‐Lecture PCProcessorDesignProcessorDesignFivestepstodesignayzeinstructionsetSelectsetofdatapathclockmethodologytherequirements yzeimplementationofeachinstructiontodeterminesettingofcontrolpointsthateffectstheregistertransferAssemblethecontrol Summer2012‐‐Lecture CS617的21PurposeofPurposeofopcode rdfunct_sel ALUctrMemWrSummer2012‐‐LectureMIPS‐liteMIPS‐liteInstructionRegisterTransferLanguageelsePCPC+4 Summer2012‐‐Lecture MIPS‐liteMIPS‐liteControlSignalsControlALUsrc=RegB,ALUctr=“ADD”,RegDst=rd,ALUsrc=RegB,ALUctr=“SUB”,RegDst=rd,ALUsrc=Imm,ALUctr=“OR”,RegDst=rt, ALUsrc=Imm,ALUctr=“ADD”,RegDst=rt,ExtOp=“Sign”, ALUsrc=Imm, ALUsrc=RegB, Summer2012‐‐Lecture10100000001010001100XX0011100001XX111100000010000001XX011XGeneratingGeneratingBooleanIdea#1:TreatinstructionnamesasBooleanUsegatestogeneratesignalsthatare1whenitisaparticularinstructionand0otherwisebeq=Rtype=add=Summer2012‐‐LectureGeneratingGeneratingBooleanIdea#2:Useinstructionvariablestogeneratecontrolsignals–Makeeachcontrolsignalthecombinationofallinstructionsthatneedthatsignaltobea1MemWrite=RegWrite=add+sub+ori+Whataboutdon’tcares–Wantsimplerexpressions;settooftableSummer2012‐‐LectureControllerControllerUsethesetwoideastodesign “OR”Summer2012‐‐LectureANDANDControlLogicinSummer2012‐‐LectureORORControlLogicinSummer2012‐‐LectureGGCProram(AMachineLaPrgam01011000010101(e.g.blockLogicCircuitD(Circuit CS617的21SetupTime:howlongtheinputmustbestablebeforetheCLKtriggerforproperinputHoldTime:howlongtheinputmustbeaftertheCLKtriggerforproperinput“CLK‐to‐Q”Delay:howlongittakestheoutputtochange,measuredfromtheCLKSummer2012‐‐LectureTheCriticalTheCriticalThecriticalpathisthelongestdelayanytworegistersinaTheclockperiodmustbelongerthanthiscriticalpath,orthesignalwillnotpropagateproperlytothatnextregister3241+Summer2012‐‐LectureCriticalPathCLDelay+CLDelay+CLDelay+AdderumumClockWhatisthemaxfrequencyofthis–LimitedbyhowmuchtimeneededtogetcorrectNextStatetoRegisterMaxDelay=Setup+CLK‐to‐Q+CLMaxFreq=1/MaxSummer2012‐‐Lecture OldOneCompleteCycleforNewRegWrRdRs RwRaRbbusASetup Summer2012‐‐LectureClockingClocking............Storageelements(RegFile,Mem,PC)triggeredbysameclockCriticalpathdetermineslengthofclockThisincludesCLK‐to‐QdelayandsetupSofarwehavebuiltasinglecycleCPU–entireinstructionsareexecutedin1clockcycleUpnext:pipeliningtoexecuteinstructionsin5clock Summer2012‐‐Lecture Rs,Rt,Rd,Op,OneCompleteCycleforNewInstructionMemoryAccessOldOldNewNewValueOldbusA,OldOldRegWrRd NewRegisterFileAccessTimeNewValueALUN